JPH021619A - Digital pll device - Google Patents

Abstract

PURPOSE:To obtain a device which is not influenced by the temperature change of a periphery, or the secular change and the like by measuring the period of an input signal through the use of a reference clock and outputting digital data which is accompanied by the period of the input signal. CONSTITUTION:The zero cross detection circuit 4 of a micro processor 1 detects the zero cross point 100 of a commercial frequency signal (a) and supplies a signal C to an interruption control circuit 5. A timer 6 counts the clock (d) of a frequency-divider 7, and supplies a signal (f) to the interruption control circuit 5 when the value of the clock (d) reaches an overflow set point (e) which decides the basic generation interval of a data output. When the circuit 5 receives the signal C or the signal (f), it adds an interruption signal (g) to a data processing circuit 8. A counter 9 counts the clock (d) until it receives a stop signal (h) from when it receives a start signal (h). With generating digital data (b) which is synchronized with the commercial frequency signal (a), the device which is not influenced by the temperature change and the like can be obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention is a digital PLL (phase-locked loop) that generates digital control data in synchronization with a commercial frequency etc. in an industrially applied electronic control device. It is related to the device.

(Prior art) PLL devices are used in communications, electric power, and all other electronics fields. For example, in the electric power field, they are used to operate electric motors in synchronization with commercial power supplies, control uninterruptible power supplies, etc. It is used for.

A typical PLL device that has been used in the past has been an analog type that uses a voltage controlled oscillator (VCO).

(Problems to be Solved by the Invention) Although this analog PLL device has a simple configuration, it has a problem in that characteristics shift and performance deteriorates due to temperature changes in component parts, aging, etc.

The present invention was made to solve the above problems, and is a digital PLL that does not change its characteristics due to temperature changes, aging, etc., and can realize highly accurate frequency synchronization with little jitter. The purpose is to obtain equipment.

[Structure of the invention]

(Means for Solving the Problems) A digital PLL device according to the present invention includes means for generating a reference clock, means for measuring the period of an input signal using the reference clock, and a large number of devices that follow the input signal. means for storing digital signal data; dividing the measured period of the input signal by the number of pieces for one period of the digital signal data, and adding 1 between a first time interval corresponding to the quotient; means for allocating a second time interval corresponding to the value of the input signal within the input signal period in a number ratio determined according to the remainder of the division, and according to this allocation, the first time interval or the second time interval and means for sequentially outputting the digital signal data.

(Function) In the present invention, the period of the input signal is measured using a reference clock, and digital data that follows the period of the input signal is output according to the principle of PLL. As a method of following the input signal, a method is adopted in which the digital output period is compensated for by using the number of digital data outputs as a parameter. In this case, if the tracking output period is divided by the number of pieces of digital data for one period, and all data for one period is output at each first time interval corresponding to the quotient of this division, the remainder of the above division will be The output data period becomes shorter than the input signal period by a corresponding amount of time, and frequency synchronization cannot be achieved properly. Therefore, in addition to the first time interval, a second time interval corresponding to the value obtained by adding 1 to the above quotient is also adopted, and the first time interval and the second time interval of the number according to the system are used. Intervals are allocated within the input signal period, and digital signal data is sequentially output at the allocated time intervals. As a result, the time difference due to the system is compensated for by the second time interval, the input signal period and the output data period match well, and extremely accurate frequency synchronization is realized.

(Embodiment) FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. This is used to control motors, uninterruptible power supplies, etc. that operate in synchronization with a commercial power supply, and includes a microprocessor system 1 driven by a high-resolution clock d from a crystal oscillator 3. This microprocessor system 1 functions to input a commercial frequency signal a from the outside and generate sine wave data b synchronized with it, and the output sine wave data b is converted into analog sine data by a D/A converter 2. converted into a wave signal.

To explain the main components of the microprocessor system 1, a zero cross detection circuit 4 detects a zero cross point 100 of the commercial frequency signal a from negative to positive, and sends a zero cross signal C to the interrupt control circuit 5. give. Further, the timer 6 counts the clock d divided by the frequency divider 7,
When the count value reaches an overflow setting value e that determines the basic generation interval of data output, an overflow signal f is applied to the interrupt control circuit 5. When the interrupt control circuit 5 receives the zero cross signal C or the overflow signal f, it applies an interrupt signal g to the data processing circuit 8.

The counter 9 counts the clock d frequency-divided by the frequency divider 7 from when it receives the start signal from the data processing circuit 8 until when it receives the stop signal. As will be described later, this count time coincides with the commercial frequency period TI, so the counter 9 measures the commercial frequency period T by converting it into the number of clocks, and the count value (commercial frequency period T,) is The data is read into the data processing circuit 8. The data processing circuit 8 is executing a main routine for commercial synchronization,
Using the zero loss interrupt and the interrupt signal g associated with the timer overflow interrupt, sine wave digital data b synchronized with the commercial frequency signal a is generated.

This microprocessor system 1 generally operates as follows. The counter 9 is operated using the zero loss interrupt C, and the commercial frequency period T1 is read.

Then, from this value, the basic interval for digital data generation is determined, and in order to finely adjust this value, it is set in timer 6.
It outputs sine wave digital data b that follows the commercial frequency signal a while generating an overflow interrupt, and its detailed operation will be explained below with reference to the time chart of FIG.

In principle, frequency synchronization is a cycle T that follows the commercial synchronization signal T1 measured by the counter 9. This can be achieved by generating sine wave digital data. In case of rice,
If the number of digital data generated for one period is N, then synchronization is achieved by generating digital data every T/N.

Here, highly accurate frequency synchronization is achieved using a method that further improves this principle, and specifically, it is performed as follows.

As mentioned above, the timer 6 has an overflow interrupt function, and this function is used to set the generation interval of sine wave data.

Now, suppose that an 8-bit counter is used as the timer 6, and the overflow setting value is set as e, as follows.

however T: Follow-up frequency period N: Number of sine wave data It is.

The timer 6 increments the count value each time the frequency-divided clock d is input, and when the value reaches the overflow value 256, it generates an overflow signal f.

In other words, the timer 6 generates an overflow signal f every time T/N, which is obtained by dividing the follow-up frequency period T by the number N of sine wave data, and outputs the sine wave data b within this period.

In this way, if N pieces of sine wave data b for one period are sequentially output for each N division value T /N of the tracking frequency period T while using an overflow interrupt, in principle,
The length of one period of the sine wave data b is approximately the commercial frequency period T1
should match, and frequency synchronization should be achieved.

However, when the commercial frequency period T is divided by the number of data pieces N, it is not always completely divisible and there is usually a remainder, but since only integers can be set in timer 6, this remainder is rounded down and becomes the quotient of the division. only is set in the timer 6 as an overflow setting value e.

For this reason, a shift occurs between the periods of the human output signals by the number of clocks corresponding to the above order, and a phenomenon occurs in which the commercial frequencies cannot be accurately matched.

This embodiment provides a means for accurately matching frequencies in such a situation.

That is, the number of bits corresponding to the above-mentioned remainder ((TLO)' in equation (3) below) is known and the data generation interval is adjusted to compensate for it.

Now, the commercial frequency period is T1, and the clock is 1μse.
If the sine wave digital data output period T to be tracked is expressed in 16 bits using c, then T is T - (THO)
x28+[TLOI usec...(2) (THO): Value of the upper byte of the 16-bit counter (TLO): Given as the value of the lower byte of the 16-bit counter. This equation (2) is converted as follows according to the number N of data generation.

T - (THO)' XN+ (TLOI'...
(3) [TLO)'<N Here, (THO)' is the quotient of the tracking frequency period T divided by the number of data generation N, and (TLO)' is the remainder.

This equation (3) means the following. That is, when using a 1 μsec clock with high resolution, (
Although N pieces of digital data are generated at the basic data generation interval of μSee, among them [TLO
]' times, with a generation interval of (THO)' +1 μsec, it is possible to accurately match the commercial frequency period T and the data generation period l T without causing any overlap.

Now, set the data generation interval to wave 11' with less distortion.
In order to realize (THO)' μsec and [T
HO]' +1 μsec are evenly interwoven. As this method, [THO)' and l
A possible method is to calculate the occurrence ratio of :THOI'+1 using a calculation formula according to the value of THOI'. That is, the occurrence ratio m is determined according to the following formula.

m: 1=N-(TLO)' : (TLOI'
o<(TLO)' ≦N/2 ] :m-N-(TLO)' : (TLOI'
N/2<[TLOI'<N 1, when calculating m using the above formula, m can only take integer values, so the decimal places are rounded down, and rTHO
)' and (THO)' +1, resulting in an error in the occurrence ratio, making it impossible to achieve accurate T.

Therefore, in this embodiment, instead of using the above method, CTHO)'
, [THOI'+1] A table predetermining the generation order is stored in a ROM, and digital data is output according to this table to realize highly accurate frequency synchronization.

Specifically, when the tracking period T is determined, [
A table is prepared for each TLO]' and output is generated according to this table.

The format of this table is shown in FIG. As mentioned above (
TLO)' is the basic data generation interval [THO]' plus 1 (THOI' + 1 interval), so among the N "0" data, (THO)'
It is only necessary to prepare a table in which "1" is substituted for the occurrence gap of +1.

Needless to say, the order in which "1's" are generated is uniformly distributed so as not to cause distortion in the output waveform.

It is sufficient to prepare as many tables as (TLO)', that is, N tables from 0 to N-1.

By preparing only one pattern of these N tables, it is possible to set the follow-up output period for any follow-up frequency period T. The reason for this is that even if T changes significantly according to equation (3), the only thing that changes is the value of [THO:l', and the remainder (TLO)'
This is because it remains in the range O≦(TLO)′<N. 4 and 5 are flowcharts showing the processing procedure of the data processing circuit 8 for realizing the above contents.

The data processing circuit 8 normally executes the main routine shown in FIG. 4(a).

In this main routine, the follow-up sine wave digital data output period T is calculated based on the commercial frequency period measurement value T and the advance and delay status of the own station sine wave digital data output signal.
Increase or decrease. The cycle 51 measurement value T of the commercial frequency to be initially tracked is measured using a zero loss interrupt.

That is, in FIG. 1, during execution of the main routine,
Every commercial frequency period T, the zero cross detection circuit 4 generates a zero cross signal, and in response to this, the interrupt control circuit 5 applies a zero loss interrupt signal g to the data processing circuit 8. When this interrupt occurs, the data processing circuit 8 executes the fourth [Z(b) routine].

In this case, a stop signal is issued from the data processing circuit 8 and the counting operation of the counter 9 is stopped.
), the count value at that time is the commercial frequency period T, [7] and is read into the data processing circuit 8 (step 302). Then, an activation signal is immediately issued and the counting operation of the counter 9 is restarted (step 303). That is, the counter 9 is stopped/started at every zero cross point 100, and the number of clocks d counted during that period is taken into the data processing circuit 8 as the commercial frequency period T.

The data processing circuit 8 slightly increases or decreases [TLO]' in equation (3) in order to follow this commercial frequency period T+. Normally, tracking is performed with an accuracy of 1 μSee. As a way to follow
First, frequency tracking is performed, and then phase tracking is performed. The frequency tracking method calculates the difference between the commercial frequency period T5 and the current tracking output period T, and continues l:TL until the difference reaches a predetermined value.
o)' is incremented by 1 (step 201), and since the method is self-evident, its explanation will be omitted here.

Next, phase synchronization will be explained. Phase synchronization is performed by increasing or decreasing TLO: l' depending on whether the commercial frequency signal a leads or lags the sine wave digital data output data b in phase. Counter 9 at the time of outputting the digital data of
For example, as shown in FIG. 6 b1, the value 103 of the counter 9 at the time of outputting the 0th digital data is determined as follows: , is smaller than 1/2 point 102 of the commercial frequency period, it is determined that the commercial frequency signal a is ahead of the sine wave digital data b. On the other hand, as shown in FIG. 6b2, the value 104 of the counter 9 is at point 10, which is 1/2 of the commercial frequency period T.
If it is larger than 2, it is determined that the commercial frequency signal a lags behind the sine wave digital data b. Commercial frequency signal a
is ahead of the sine wave digital data b,
In order to advance the sine wave digital data b, (T
LO)' is subtracted by 1 (step 203).

In addition, commercial frequency No. 15 a is sine wave digital data b
If it is delayed, 1 is added to (TLOI' in equation (3)) to delay the sine wave digital data b (step 204).Here, by increasing or decreasing (TLO)',
(TLO)' becomes equal to N, or -1
If it is, update the value of the upper [THO]' and set it to 0.
Adjust to ≦(THO)'<N. In any case, (TLO)' is finally determined, and the table access start address for adjusting the output data generation gap is determined (step 2
05). The start address of the table to be accessed is, for example, the start address when CTLO)' -0 is TB.
If L O, TBL (TLO)' - TBL O+NX (TLOI'...(4)
It can be found by

The main routine passes the value of the table access start address obtained here and the value of the basic data generation interval [THO)' to the overflow interrupt routine via the data transmission RAM area.

Next, an overflow interrupt routine that determines the output data generation interval will be described.

As shown in Figure 5, when an overflow interrupt occurs,
First, a data generation number is checked (step 401). If this data generation number is the final data + 1, the data generation number and ROM data readout number are cleared, and the value of counter 9 is read and passed to the main routine (step 402). As described above, the main routine uses this value to determine lead/lag.

next. The main routine outputs sine wave digital data b corresponding to data generation number SN (step 403).
). Next, the interrupt routine corrects the basic data generation interval (THO)' using the basic data generation interval determined by the main routine and then transmitted via the information transmission RAM area and the table access start address data. I do. That is, the ROM data is read using equation (4) and the table data readout number TN (step 404), and if the data is zero, it is left as (THO)' (step 405), and if it is 1, it is (THO). )' +1
(Step 406). This value is expressed as T in formula <1>
/H is substituted, the overflow setting value e is obtained, and it is set in the timer 6 (step 407). Finally, 1 is added to each of the data generation number SN and ROM table reference number TN (step 408), and this routine ends.

Thereafter, the same operation is repeated every time an overflow interrupt occurs until the final data is output. That is, based on the basic data generation gap passed from the main routine by a timer overflow interrupt, the basic data generation gap is adjusted while referring to the ROM table data, and sine wave digital data is output one after another. .

As a result, data is generated at intervals of [TLO)' +1 μsec a number of times corresponding to the remainder (TLOI') of the above division, and as a result, the remainder (TLO)'
This compensates for the period shift caused by the oscillation, and outputs sine wave data with accurate frequency synchronization.

Here, if we talk about the tracking accuracy, for example, 50
When a commercial frequency of Hz is counted with a clock of 1 μsec, it becomes a value of 2000 counts, which means that the method of the present invention follows this value with an accuracy of ±1 count.

Although the present invention has been described above with reference to preferred embodiments, it goes without saying that the present invention is not limited to a microprocessor system, and can be realized by a one-chip microcomputer that integrates a microprocessor, a counter, a timer, and an interrupt processing circuit.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, since digital processing is performed using a reference clock, a stable PLL device that is not affected by changes in ambient temperature, aging, etc. can be obtained.

Furthermore, since the digital data generation interval is adjusted using the minimum resolution of the period measurement clock, highly accurate frequency synchronization with little jitter can be achieved.

Furthermore, by performing PLL processing using software processing by a microprocessor, there is an advantage that only a small number of parts are used, and the PLL-based device can be made compact and small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of frequency synchronization by adjusting the data generation interval, and FIG.
The figure is an explanatory diagram of the configuration of the main elements of the same embodiment, FIG. 4(a),
(b) and FIG. 5 are flowcharts for explaining the operation of the same embodiment, and FIG. 6 is a time chart for explaining the operation of the same embodiment. 1...Microprocessor system, 2...D/A
Converter, 3... Crystal oscillator, 4... Zero cross detector, 5... Interrupt control circuit, 6... Timer, 7...
Frequency divider, 8... data processing circuit, 9... counter. Applicant's agent Sato - Male TBL - 〇 1. 3. 2. 4. 5.

Claims (1)

[Claims] means for generating a reference clock; means for measuring the period of an input signal using the reference clock; means for storing a large number of digital signal data that follows the input signal; A first time interval corresponding to the quotient and a second time interval corresponding to a value obtained by adding 1 to the quotient are divided by the number of digital signal data for one cycle, and a first time interval corresponding to the quotient is calculated according to the remainder of the division. and means for sequentially outputting the digital signal data at the first time interval or the second time interval according to the distribution within the input signal period in a number ratio determined by Digital PLL device.