JPH0216464A - Decision system for distribution line accident detection phase - Google Patents

Abstract

PURPOSE:To accurately output a decision result even when a phase angle can not be detected or in the case of waveform absence or a multiple accident by storing the phases of a voltage and a current in a memory in order and conducting a majority decision test of the number of leading or delayed memory contents. CONSTITUTION:A sensor 2 detects an analog current signal and a voltage signal and input them to waveform forming circuits 7A and 7B through a transformer 5 and a filter 6. One of their rectangular wave output signals is inputted to an input signal decision circuit 9 directly and the other output is inputted through an A/D converter 8 to detect the phase from the rectangular wave output signal and also decides whether or not the detected phase signal is effective according to the output of the A/D converter 8. Then the result is stored in the memory 12 and the leading or delay of the phase angle is decided by majority from the stored phase signals to accurately decide the phase even when the phase varies with time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in the FC Industry] The present invention relates to a phase determination method for processing 41 error information in a power distribution line.

[Prior Art] Conventionally, the voltage and current waveforms at the time of a ground fault fault in a faulty distribution line, such as an insulator arc or a cable arc, often exhibit a steep pulse shape, and high frequency noise and pulse fault current are often Generally, a CR type analog integration circuit consisting of a capacitor C and a resistor R is used to screen and determine an accident.

[Problem to be solved by the invention] However, in this CR type analog integrating circuit, its own 11
In cases where the phase of voltage or current fluctuates over time due to a phenomenon, it is difficult to accurately determine the phase.

An object of the present invention is to provide a technology that enables phase determination for fault detection in power distribution lines through digital processing using a computer.

The present invention also attempts to determine the phase of steep voltage and current at the time of ground fault 1 (failure) accompanied by 611 child arc or cable arc, and the phase of voltage and current changes over time due to the accident phenomenon. It is an object of the present invention to provide a technique that enables accurate phase determination even when the phase fluctuates.

A further object of the present invention is to provide a technology that can detect failures even during power outages and can also respond to multiple accidents.

Other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application, including their embodiments, and their main effects is as follows.

In other words, in the present invention, the phase of the rectangular wave that continues from the zero crossing of the detected voltage and current is compared, and the phase signal is stored in the computer as a digital signal for each cycle of the detected waveform, and the phase advance or Delay determination is performed by calculating the number of advances or lags in the memory contents using a computer and using a polygonal method.

In this way, since the memory contents are subjected to a majority vote test, even if it is not possible to determine whether the phase angle is leading or lagging, or if a half-wave waveform is completely missing due to a missing waveform, the memory contents can be stored accordingly. a, and if the memory contents before and after that can be determined to be ahead or behind by majority vote, the determination result can be accurately output by computer calculation.

-1- The polydisperse test can be performed in real time or after a power outage.The former method stores new information in an endless ring memory and deletes the oldest information first. Then, the contents from the latest information newly stored in the memory up to a certain number of memories are sent to the computer to make a majority decision p1. When the result of the majority decision is zero or greater than zero, the computer determines that the phase angle decision is "delayed" and outputs a latch signal. This latch signal is stored in a latch memory for a suitably timed period during which a fault indication is required;
After the time limit has elapsed, the contents of the latch memory are erased. However, if the accident continues, the latest information will send phase angle "delay" information indicating that there is an accident to the computer one after another, and the computer will perform a majority vote test, and if the result is zero or greater than zero, The latch signal is sequentially output with the phase angle determination being "delayed".

The present invention also relates to a method that enables LI failure detection even during a power outage. A majority vote test is performed on the memory contents going back to the beginning.

With this test, even if a power outage occurs within half a wave from the occurrence of an accident, it is possible to detect a 1■ failure.
It can also respond to multiple accidents.

[Example] Next, the present invention will be explained with reference to drawings showing embodiments thereof.

FIG. 1 shows an embodiment of a circuit diagram of a digital phase determination processing circuit used in the present invention.

Here, the digital phase determination processing circuit 1 is connected to a sensor 2 having connection terminals I-3 and 4 and a transformer (CO
M) 5, filter 6, waveform shaping circuit 7, analog/digital conversion circuit (device) [A/D converter] 8, input signal judgment circuit 9, driver≠10, buffer 1 [and endless memory element-1-12] It comprises a display device γj13, a central processing unit ff(C!'LJ)l4, a nonvolatile memory element 15, a buffer 16, a power outage detection circuit 19 consisting of a relay circuit 17 and a rectifier circuit 18.

Further, in FIG. 1, S represents a power source.

The sensor 2 is composed of, for example, a transformer or a current transformer, and is installed on the distribution line; be done.

The human input analog current signal (io) detected by the sensor 2 is input to the COM 5 via the connection end f3, and at the COM 5, the signal 1° is converted to a predetermined level.

The human-powered analog voltage signal (V, ) detected by the sensor 2 is manually inputted to COM 5 via the connection terminal 4, and the voltage signal (V) is generated at COM 5. is converted to a predetermined level.

Here, these two input analogs (A 'i +
.

This is an example for V.

” - conversion is performed using these human-powered analog signals 1°, v.

is converted into an analog signal of a predetermined amplitude.

The filter 6 is designed to pass only analog signals with a certain band frequency.

The waveform shaping circuit 7 detects the zero cross of the human input analog signal 1°, vo output from the filter 6, and outputs a rectangular wave output signal clipped to a constant amplitude.

FIG. 2 shows examples of waveform diagrams and timing charts in the present invention.

FIG. 2(A) shows the same 7Δ of the waveform shaping circuit 7 written in −.
The figure (b) shows the case where the input analog signal △゛, which was manually inputted in 713, is ahead of the input analog signal 〛13゛ in phase A1, and the input analog signal △゛ is in the same direction. A case is shown in which the signal B' is ahead of the human input analog signal Δ'.

As shown in FIG. 2(A), the waveform shaping circuit 7△713 detects the zero cross of these human-powered analog signals 20△'2013' and outputs the output signal 2 clipped to a constant amplitude.
Outputs +A and 21B.

In addition, in the following description, explanation will be given in a comprehensive manner including (1) for convenience (1) and (1) above.

As shown in FIG. 1, the output of one of the waveform shaping circuits 7A and 713 is sent directly to the input signal T+1 constant circuit 9 without going through the Δ/D converter 8.

Further, the outputs of the other waveform shaping circuits 7 Δ and 713 are sent to a human input determination circuit 9 via a Δ/I) converter 8 .

Δ/1) The converter 8 digitally converts the amplitude of the output signal of the waveform shaping circuit 7.

The input signal p1 constant circuit 9 is an integrated circuit including an AND circuit and an OR circuit, and compares the phases of the rectangular wave output signals of the waveform shaping circuit, and outputs the output waveform A shown in the waveform example in FIG.
, B AND signal 22°OR signal 23. From the rising edge of the OR signal 23 to the falling edge of No. 4 22 in the ΔNo
Continuing displacement point signal 24. A comparison between the signal 24 and the output signal of the waveform shaping circuit 7A 1) A No. 8 25. Displacement point signal 2
4 and the output signal of waveform shaping circuit 7B and (+) A N
I) make signals 26 and these AN +) signals 25.26
and the AND signal 27.28 of the clock signal,
゛hThe human input signal (drives the flip-flop circuit (hereinafter sometimes referred to as 1K flip-flop) built in the judgment circuit 9.The flip-flop circuit drives the flip-flop circuit (hereinafter sometimes referred to as 1K flip-flop). A counter (not shown) counts the clock frequency, and a down counter (not shown) counts the clock frequency by the duration of the 2L signal 28.

The Δ/1) converter e detects the level of the output signal of the waveform shaping circuit 7, performs Δ/D conversion, and sends the digital signal (No. 4) to the input signal determination circuit 9.

In the input signal judgment circuit 9, which is made up of a gate array containing an AND circuit, an OR circuit, and a JK flip-flop,
Valid (No. 14 (V△1.I D
) is sent to the JK flip-flop, and the flip-flop is set [(29) to (30) in FIG. 2].

The flip-flop stores data counted by the up counter (hereinafter referred to as "up count data").
, the data counted by the down counter (hereinafter,
When the calculation result is positive, it is a positive pig, and when it is negative, it is a negative data, CI
) tJ l 4 [Figure 2 (29) to (31
)] - CI) U l 4 is the positive data 32 or the negative pig 33 sent out from the input signal determination circuit 9 as shown in FIG.
are successively stored in the endless memory element 12 (35), and new input data is written in by sequentially erasing the old and circulating memories.

-・The total number of addresses in the circular endless memory 35 is 500.
The total number of memory addresses when inputting from the two-channel waveform shaping circuit 7 is 2x500=1000.

When the output of the A/D converter 8 exceeds a predetermined value set in the non-volatile memory element 15, CP tJ l 4 starts counting the number of +E and negative data of the signal input to the endless memory element 12, and When counting only a number (for example, 11), a majority test is performed on the number of positive and negative data. In the case of 11 data test, when the number of positive data is greater than the number of negative data (6 or more), Assuming that an accident has occurred, the CI) IJ l 4 drives the driver 10 via the input signal determination circuit 9, and causes the display device η13 to display that there is an accident.

Since the data in the endless memory element 12 is rewritten for each half wave of the input signal, the majority test is performed for each half wave.

A wave drop occurs in the input signal, and the endless memory element 12
When the human input data (X) 34 in which the memory 35 in the memory 35 cannot determine p1 whether positive or negative is sent to the input signal judgment circuit 9, the input signal judgment circuit 9 converts the unstable signal (F F: ) into CP.
Send to U14.

When the unstable signal FF is included in the memo 35 of one square constant for testing, the CPU 4 calculates an effective signal excluding these unstable signals 1' F in the predetermined testing number circle. A majority test is performed based on the number of memories 35.

The majority vote test makes a positive determination when there is a large number of city data or when the numbers are equal.

CI) 1114, if a valid iE or negative test is performed during the predetermined memory number test, one of the test contents
[Or, store a negative signal in a predetermined location of the endless memory element 2 (hereinafter referred to as accident verification memory), and set an appropriate time period within the period when a valid input signal is occurring or after the input signal stops +h (hereinafter referred to as F time period) During this period, the contents of the verification memory are held without being changed. When the I&F time period (for example, 5 seconds) in which no valid input signals are present has elapsed, the contents of the I/F test memory are erased. At this time, the endless element 12 continues to make three new changes to the memory contents.

This I? When the power failure detection circuit 19 detects a power failure within the time limit, the relay circuit 17 operates and drives the input signal p1 constant circuit 9 via the buffer 16.

The input signal determination circuit 9 sends the contents of the accident verification memory of the CPU I 4 to the driver IO and displays them on the display device 1:3.

In another embodiment of the present invention, when the power failure detection circuit 19 detects a power failure within the F time period and the relay circuit 17 drives the input signal determination circuit 9, the input (A'j determination circuit 9 detects CP LJ
The power is cut off to change the contents of the endless memory card 35 of the CPU 14, and the CPU 14 is instructed to carry out a majority vote check on the memory contents 35 retroactively from the time of the power failure. CI) [''14 performs a positive/negative majority test on the memory contents up to a predetermined number of memories from the power outage, and when the number of positive and negative data is the same except for unstable No. 13 FF, or when the number of positive and negative data is large, or when the number of 11 data is large. At this time, if the test was performed before the power outage and the negative test No. 13 is stored in the li test memo υ, the information on the historical test performed retroactively from the time of the power outage is stored. In the case of IF, priority is given, positive judgment is made, and human iA
The display panel d13 is driven through the signal determination circuit 0 and the driver 10, and a determination of +[E (!IN fault exists) is displayed.

- 11 Therefore, when the content in the verification memory is negative or zero, the input signal determination circuit 9 does not respond, and the driver 10 does not drive the display device 1:3.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application can be briefly explained as follows.

According to the present invention, it is possible to accurately determine the phase of steep voltages and currents during ground faults involving insulator arcs and cable arcs. The phase can be determined accurately even when the phase of
We were also able to deal with multiple accidents.

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and may be modified in various ways without departing from the gist thereof. Needless to say.

[Brief explanation of the drawing]

FIG. 1 is a circuit system diagram in an embodiment of the present invention, FIG. 2 is an operational waveform diagram in the embodiment of the present invention, and FIG. 3 is an explanatory diagram of the same operation.・Digital phase determination circuit ・Sensor ・Transformer ・Filter ・Waveform shaping circuit ・Δ/D converter ・Input signal determination circuit ・Driver ・Buffer ・Endless memory element ・Display device ・Central processing unit 1 (CPU) ・Nonvolatile memory element・Buffer, relay circuit, rectifier circuit, power failure detection circuit

Claims (1)

[Claims] 1. After converting two or more input analog signals detected by sensors installed on the distribution line to a predetermined level using a transformer, the converted analog signals are passed through a filter to pass only a predetermined frequency band. After that, it is sent to a waveform shaping circuit to detect the zero cross of the analog signal and output a rectangular wave output signal clipped to a constant amplitude.The output signal of one of these waveform shaping circuits is sent to the input signal determination circuit to The other output signal of these waveform shaping circuits is sent to the input signal determination circuit via the analog/digital conversion circuit, and the output signal of the other waveform shaping circuit is sent out directly without going through the digital conversion circuit. The displacement point signal that continues from the rise to the fall of the AND signal and the OR signal obtained by the output signal of A counter is driven and counted by a clock frequency to obtain count data, and a storage device (hereinafter referred to as this storage device) stores the positive or negative polarity depending on whether the difference between the count data is positive or negative. At the same time, the other output from the waveform shaping circuit is converted into a digital signal proportional to the amplitude of the other output signal in the analog/digital conversion circuit, and is then input to the input signal determination circuit. The input signal determination circuit compares the digital output signal of the analog/digital conversion circuit with a threshold value stored in a non-volatile storage device (hereinafter referred to as a non-volatile memory element), and determines whether this digital output signal is When it is larger than the threshold, the content of the endless memory element is fixed and read by the central processing unit, and the central processing unit reads the content of the central processing unit previously stored in the non-volatile memory element. A phase determination method for detecting an accident in a power distribution line, characterized in that the phases of the two or more input signals are determined by counting positive or negative polarity data out of the number of data and performing a majority test. 2. When the output of the waveform shaping circuit continues intermittently for a predetermined period of time or continuously for a predetermined period of time, the central processing unit performs a majority vote test to determine the phase of the input signal, and outputs a positive or negative signal. The specified location of the endless memory element (hereinafter referred to as
The accident test memory is stored in memory for a predetermined period of time.
2. The phase determination method according to claim 1, wherein the memory contents are erased after the predetermined time has elapsed. 3. If the central processing unit includes unstable signals in the judgment signals sent by the input signal judgment circuit, the memory addresses of these unstable signals are used as count values, and are used as the majority test number for positive/negative judgment. 2. The phase determination method according to claim 1, wherein the phase determination method performs logical calculations that do not involve the following. 4. After the central processing unit memorizes the phase determination result signal in the accident verification memory of the endless memory element, it is stopped by a signal from the power failure detection circuit within a predetermined time and then sends the phase determination result of the accident detection memory to the display device. 2. The phase determination method according to claim 1, wherein a display to that effect is provided. 5. When the central processing unit detects a power outage within a predetermined time period after storing the phase determination result signal in the accident verification memory,
The central processing unit prevents and locks new information from being input to a desired address of the endless memory element, and
A majority test is performed on the number of positive and negative polarities of the memory contents going back a predetermined number of addresses from the address where information was most recently memorized, and if the test result differs from the contents of the accident test memory stored earlier, the contents of the accident test memory are updated. 2. The phase determination method according to claim 1, wherein the signal is rewritten to a signal of the majority test result and drives a display device via a driver.