JPH0216473A - Mode setting circuit - Google Patents

Abstract

PURPOSE:To prevent a mode setting circuit from causing a malfunction due to noise from an input terminal by controlling a transfer gate by a clock and a counter at the time of resetting, so that a mode setting input can be executed by a prescribed time. CONSTITUTION:The title circuit is provided with a counter 2 to start count of a clock signal by a reset signal R, and by connecting its output to a clock control circuit 5, it is controlled to supply the clock signal to the counter. Also, a mode setting input terminal P is connected to a latching circuit 1 through a transfer gate 3, and its output goes to an integrated circuit internal mode setting signal. Also, said circuit is constituted so as to control the transfer gate 3 by the output of the counter 2. In such a way, only for a prescribed time determined by the output of the counter after the reset, a mode setting signal can be inputted through the transfer gate, and it can be prevented that noise is mixed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mode setting circuit, and more particularly to a mode setting circuit built into an integrated circuit for switching the operating mode of an internal circuit of the integrated circuit.

[Conventional technology]

Traditionally, the operation of integrated circuits has been divided into several operating modes.
The operating mode of the device is changed depending on the conditions of use and the like. For example, if you need to check whether an integrated circuit is working properly, you can stop the operating mode under normal use and switch to test mode to check the operating status of the integrated circuit. A mode setting circuit is provided for setting a test mode. Then, whenever necessary, a mode setting circuit is used to switch the operating state of the circuit from the normal operating mode to the test mode and perform a test.

An example of this mode setting circuit is a three-level voltage signal (for example, OV) as the input voltage value.

There is one that is provided with a three-value input terminal that receives input voltages (+5V, +10V). In the operating mode under normal usage conditions,
A binary voltage (for example, OV, +5V) is input to this input terminal to switch the circuit operation, but when you want to switch to the test mode and perform a test to check the circuit operation, you can input the 3-value voltage to the input terminal. Input the value voltage (+10V).

When the third value voltage (+10■) is input, the test mode setting circuit distinguishes this voltage from other voltages and sends a test mode setting signal to the internal circuit of the integrated circuit. It is now possible to switch the circuit to a test mode state.

[Problem to be solved by the invention]

The conventional mode setting circuit described above inputs the third value input voltage in order to switch modes, so the manually input third value voltage (+10V) may change to other voltages (0 or 0V) due to external noise etc. +5V) If the voltage changes to a value close to +5V, the desired mode cannot be switched due to a malfunction, or if the circuit is operated by inputting either of the two voltages (OV, +5V). Another problem is that if a voltage close to the third value (+10V) is generated due to external noise, the current operating mode will switch to another operating mode (test mode in the above example). there were.

The purpose of the present invention is to prevent the mode setting circuit from malfunctioning due to noise from the input terminal after the internal circuit of an integrated circuit starts operating in a set operating mode, and the operating mode of the internal circuit changes. The purpose of the present invention is to provide a mode setting circuit that never fails.

[Means to solve the problem]

(A) The mode setting circuit of the present invention is controlled to an initial state by a reset signal input from a reset signal input terminal, receives a clock signal, counts the clock signal, and calculates the frequency of the clock signal. (B) a counter that sends out a frequency-divided output signal; an internal reset control circuit that receives the output signal of the counter and stops sending out a signal for resetting internal circuitry of the integrated circuit;
(C) a clock control circuit that receives the clock signal and the output signal of the counter and controls sending and stopping the sending of the clock signal based on the output signal of the counter; (D) converting the output signal of the counter into a gate signal; a transfer gate that receives the mode setting signal input from the mode setting input terminal and controls sending the mode setting signal input to the internal circuit of the integrated circuit and stopping the sending using the output signal of the counter; (E) inputting from the reset signal input terminal; and a latch circuit that receives and holds the mode setting signal sent from the transfer gate, and sends the mode setting signal to the internal circuit of the integrated circuit. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The mode setting circuit shown in FIG. 1 includes a counter 2 that receives and counts a clock signal and sends out an output signal 9 obtained by dividing the frequency of the clock signal, and a reset signal that is input from a reset signal input terminal R and integrates the counter 2. A reset control circuit 4 that sends an integrated circuit internal reset signal to the internal circuit of the integrated circuit for resetting the internal circuit of the circuit, receives the output signal 9 of the counter 2, and stops sending out the integrated circuit internal reset signal, and a clock. A clock control circuit 5 receives the signal and the output signal 9 of the counter 2, and controls sending and stopping of the clock signal based on the output signal 9 of the counter 2, receives the output signal 9 of the counter 2 as a gate signal, and controls the mode. A P-type transfer gate 3 that controls sending of the mode setting signal input from the setting input terminal P to the internal circuit of the integrated circuit and stopping the sending of the mode setting signal using the output signal 9 of the counter 2.
, a latch circuit 1 that receives and holds a mode setting signal sent from a P-type transfer gate 3, and sends the mode setting signal to an internal circuit of the integrated circuit.

Next, the operation will be explained.

The reset signal given to the reset input terminal R is rL
ow'' level (hereinafter referred to as ``L'' level) resets the internal circuit of the integrated circuit.
(hereinafter referred to as "H" level), the reset state is released.

Further, the mode setting signal applied to the mode setting input terminal P puts the internal circuit of the integrated circuit into a normal operating state at the "L" level, and puts it into the test mode state at the "rH" level.

FIG. 2 is a waveform diagram showing the circuit operation of FIG. 1.

First, an external reset signal is input to the reset signal input terminal R.
, the reset signal is input to the J set control circuit 4. At this time, when the signal level of the reset signal is set to [LJ level and input, the reset control circuit 4 composed of NAND outputs the integrated circuit internal reset signal at rH, level, and puts the internal circuit of the integrated circuit into the reset state. . At the same time, the reset signal is input to the reset terminal of the counter 2 and the reset terminal of the latch circuit 1, and the output signal 7 of the divide-by-2 circuit 6a constituting the counter 2,
The output signal 8 of the divide-by-2 circuit 6b and the output signal 9 of the counter 2 are all reset to the rL level, and the output of the latch circuit 1 also becomes the "L" level.

On the other hand, when the clock signal and the output signal 9 of the counter 2 are input to the clock control circuit 5, the output signal 9 of the counter 2
Since the clock signal is at the "L" level, the clock signal is output as is, and is output to the counter 2 together with the reverse phase clock generated by the inverter. Also, a P-type transfer gate 3 to which the output signal 9 of the rl and level counter 2 is inputted.
becomes conductive, and the mode setting signal of rH, level (indicating mode setting) input from the mode setting signal input terminal P is passed through the P-type transfer gate 3 to the latch circuit 1.
is input. However, at this time, since the latch circuit 1 is still reset, the mode setting signal of the rH level is not latched and remains at the "L" level.

Next, in order to release the reset state of the internal circuit of the integrated circuit, when the reset signal applied to the reset input terminal R is changed from the "L" level to the "I(" level), the counter 2 is released from the reset state and the clock signal is The latch circuit 1 starts counting and is similarly released from the reset state, and latches the "H" level mode setting signal that is externally applied via the mode setting signal input terminal P. , the output of the latch circuit 1 also becomes rH, level, and a mode setting signal of rH, level is sent to the internal circuit of the integrated circuit.When the mode setting signal is at "H" level, the operation mode becomes test mode. If the internal circuit of the integrated circuit is configured, after this signal is sent out, the reset state of the internal circuit of the integrated circuit is released by the integrated circuit internal reset signal, and the internal circuit of the integrated circuit enters the test mode state. However, the output signal 9 of counter 2
Since the integrated circuit internal reset signal remains at the "L" level, the integrated circuit internal reset signal also remains at the "H" level, and the reset state of the internal circuit of the integrated circuit is not released.

When the count of the counter 2 progresses and the output signal 9 of the counter 2, that is, the positive phase output of the divide-by-2 circuit 6c, reaches the rH level, the output of the clock control port F/+5 becomes the rH level, and the count of the counter 2 increases. Stop. In this state,
The output signal 9 of the counter 2 continues to be at rH level until the reset signal becomes "L" level again.

In addition, the mode setting signal may become rH due to noise, and the level may become
Even if the output changes to "L" level, the output of the latch circuit 1 continues to be at "rH" level. Furthermore, the reset control circuit 4 receives the output signal 9 of the "I(" level) of the counter 2, and outputs the integrated circuit internal reset signal of the "L" level to release the reset state of the internal circuit.This causes the mode setting. According to the signal, the internal circuit enters the test mode state.

- Once the test mode is entered, this state is maintained until it is reset again and the reset state is released.

The mode setting can be changed only after the reset state is entered and when the reset state is released and the counter 2 output signal 9
This is within the time it takes for the voltage to reach the rH level, and the shorter this time, the fewer malfunctions due to noise and the like will occur. Furthermore, by increasing the number of stages in the divide-by-2 circuit of the counter, the time during which mode settings can be changed can be extended.

In this way, by allowing the mode setting input for a limited fixed period of time, after the internal circuit of the integrated circuit starts operating in the set operating mode, the mode setting circuit will be affected by noise from the input terminal. It is possible to prevent the internal circuit from malfunctioning and changing the operating mode of the internal circuit.

〔Effect of the invention〕

As explained above, the present invention adds a clock control circuit, an internal reset control circuit, a counter, and a transistor sphere gate to enable mode setting input for a limited fixed period of time. After the circuit starts operating in the set operating mode, the mode setting circuit can be prevented from malfunctioning due to noise from the input terminal, and the operating mode of the internal circuit can be prevented from changing. have

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the circuit operation of FIG. 1. ■・・・Latch circuit, 2・・・Counter,
3...P-type transfer gate, 4...
・Reset control circuit, 5...Clock control circuit, 6a to 6c...2 frequency divider circuit, 7...
Counter output signal. Agent Patent Attorney Oto Hara latch circuit 6a, 6! +: z'a8 intestine diagram 1

Claims (1)

[Scope of Claims] (A) The operating state is controlled to an initial state by a reset signal input from a reset signal input terminal, receives a clock signal, counts the clock signal, and divides the frequency of the clock signal. (B) a counter that receives a reset signal input from the reset signal input terminal and sends a signal to the internal circuit of the integrated circuit to reset the internal circuit of the integrated circuit; an internal reset control circuit that receives an output signal and stops sending out a signal for resetting internal circuitry of the integrated circuit; (C) an internal reset control circuit that receives the clock signal and the output signal of the counter; a clock control circuit that controls sending and stopping the clock signal; (D) receiving the output signal of the counter as a gate signal and transmitting the mode setting signal input from the mode setting input terminal to the internal circuit of the integrated circuit; a transfer gate that controls transmission and transmission stop using an output signal of the counter; (E) a mode setting whose operating state is controlled to a reset state by a reset signal input from the reset signal input terminal and transmitted from the transfer gate; A mode setting circuit comprising: a latch circuit that receives and holds a signal and sends it to an internal circuit of an integrated circuit.