JPH0216613A - Bias circuit - Google Patents

Abstract

PURPOSE:To prevent the differential input circuit characteristic fluctuation even when a transistor threshold voltage is changed by making prescribed the channel length and the channel width ratio of two pairs of MES FET of the serial connection to control a gate with a partial voltage. CONSTITUTION:A bias circuit A is formed by MES FETM1 and M2 of the serial connection between two constant voltage sources to control a gate with a partial voltage, and a bias voltage is supplied to the gate of MES FETM15 which becomes the constant current pource of a differential input circuit B with the connecting point of the FETM1 and M2 as an output terminal. A ratio W1/L1 of the channel length and the channel width of the FET of these gain coefficients KB1 and KB2 is made essentially four fold of a ratio W2/L2, satisfy the conditions of an expression I, and then, the current to flow at the circuit B does not depend on the threshold voltage of the FETM1 and M2. Consequently, even when the threshold voltage of the FETM1 and M2 is fluctuated, the flowing current is not fluctuated and it is prevented that the characteristic of the circuit B is fluctuated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bias circuit used for the gate of a constant current MO8FET.

[Conventional technology]

Conventionally, as a gate bias circuit for a constant current source transistor in a differential input circuit composed of MOS FETs,
A circuit as shown in FIG. 5 has been used. Detail is,"
See paper number 456, ``Evaluation of Comparator Offset Voltage,'' in the 1986 Proceedings of the General National Conference of the Institute of Electronics and Communication Engineers. Here, the P-ch MOS FET M15 is a constant current source transistor of the differential input circuit (M+x''M14), and the MOS FETs M16 and M1 constitute a bias circuit.

The gain coefficient of this transistor is expressed by the following equation, where the channel length of the transistor is multiplied, the channel width is W, the unit capacitance of the gate oxide film is Cox, and the surface mobility of electrons is μ.

= μCOX (1) L In addition, in the circuit of FIG. 5, the transistor Ml6. M
If the current flowing through the transistor M1 is
6. Since transistors M and M7 are both in the saturation region, transistors M16. The gain coefficient of M, , is expressed as follows by using 6 and F.

I = 6 (Von Ve I Vtpl)
”...(2) I=K 7 (VB VTN)
2...ku3) Here, VB is transistor M! 6. It is the voltage at the connection point of Ml7, and V TN and V 7p are respectively NMO3) transistor M! ? , P M OS is the threshold voltage of transistor M16. Calculating VB from equations (2) and (3) (VDD IVtpl)...(4) Fifth
In the differential input circuit shown in the figure, a current 5 of the following equation flows using V of equation (4).

I 5 = 5 (VDn VB VTP) 2・”
(5) However, K5 is the gain coefficient of transistor M5. Substituting equation (4) into equation (5) yields the following equation.

(VDD V'TN I V Ding PI >
2-(6) In this way, when the constant current source transistor M+5 of the differential input circuit is biased using this bias circuit, as shown in equation (6), K5. 6.
7 and the threshold voltage of the transistor V ding, , V↑P
A current that depends on the current flows through the differential input circuit.

[Problem to be solved by the invention]

In this way, when the constant current source transistor M15 of the differential input circuit is biased using the conventional bias circuit shown in FIG. 5, when the threshold voltage VTN (or Vtp) of the transistor changes, the difference dynamic input circuit (M
11 to M14) changes. Since the threshold voltage of this transistor changes depending on the dose of impurities injected into the substrate during the process, the current flowing through the differential input circuit changes due to process variations during transistor manufacturing. When the current flowing through the differential input circuit changes, the frequency characteristics of the differential input circuit and the operational amplifier circuit using the differential input circuit change, and furthermore, the characteristics of a large-scale LSI using the differential input circuit change. Therefore, even if an optimal design is performed at the stage of designing an LSI, there is a problem in that it deviates from the optimal value due to process variations, resulting in deterioration of characteristics.

An object of the present invention is to solve such problems and to prevent the current flowing through the differential input circuit from changing even if the threshold voltage of the transistor changes due to process variations, so that the circuit characteristics do not change. The purpose of the present invention is to provide a bias circuit with improved characteristics.

[Means to solve the problem]

The configuration of the present invention includes a first MES FET and a second MES FET, which have the same conductivity and each substrate is connected to each source.
MES FETs are connected in series between the first constant voltage source and the second constant voltage source, and each of these MES FETs
A bias circuit configured by supplying a voltage divided by a plurality of resistors connected in series between the first constant voltage source and the second constant voltage source to the gate of the first constant voltage source.
The ratio Wl/Ll of the channel length Ll of the second MESFET and the channel width W1 is the ratio W2/L2 of the channel length L2 and channel width W2 of the second MESFET.
It is characterized by being substantially four times as large.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram in which a differential input circuit is added to FIG. 1. In this embodiment, the first and second constant voltage sources (VDD and Vss)
Resistors R1 to R3 are connected in series between 1 and 2, and from these connection points, the first and second P-ch MES FETs are connected in series between the same constant voltage sources 1 and 2.
Connected to each gate of Ml, M2, these MES
FET Ml.

A bias voltage Vo is taken out by using the connection point of M2 as an output terminal 3.

This output bias voltage is applied to the P-ch MO, which serves as a constant current source for the differential input circuit (M11 to M14) as shown in FIG.
Supplied to the gate of S FET M15.

In Fig. 1, the transistor gain coefficient of MES FETs M and M2 is KB 1 + K 82, and the current flowing through these MES FETs Ml and M2 is IB
Then, the following formula holds true.

I a = Ket (VDD Vl l Vtp
l ) 2...(7) I n =Ka□(VOV2
1 Vtpl) 2...be♂) These (7),
When Vo is determined from equation (8), the following equation is obtained.

By the way, the channel lengths of FETs M, M2 are LBl, L, □, respectively, and the channel widths are Wllll, respectively.
1, W, and 2, the gain coefficients KBI and KB2 in this embodiment (the present invention) are as shown in the following equations.

Substituting this value into equation (9) yields the following equation.

Vo = 2 (Vno Vt) +V2 1 V
tp...(13) In this circuit, when the constant current source transistors M and 5 of the differential input circuit are biased as shown in FIG.
The current Id flowing through 5 is expressed by the following equation.

Id=5 (VDD V.-IVTPI)2=2
V I V 2 V on...(14)
As is clear from this equation, when two MES FETs are used and the channel length and channel width of these MES FETs are set in the relationship of equation (12), the current Id flowing through the differential input circuit is It does not depend on the threshold voltage of M2. Furthermore, since V, V2 are voltages obtained by resistance division, they are determined by the ratio of the resistances, and there is no need to consider voltage changes in V 1 and V 2 due to process variations. Therefore, even if the threshold voltage of the transistor changes due to process variations, the current flowing through the differential input circuit does not change. As a result, the characteristics of the differential input circuit do not change, making it possible to perform optimal design and design a high-performance integrated circuit.

FIG. 3 can be said to be a bias supply circuit in which the value of R3 in FIG. 1 is set to zero. This circuit also functions similar to the bias circuit shown in FIG.

Further, FIG. 4 shows a bias circuit in which an N-ch transistor is used as a constant current source transistor of a differential input circuit instead of driving the P-ch transistor shown in FIG. In this case, the P-ch MES FE shown in FIG.
T Ml , instead of M2, N-ch MES
FET Ms, M4 may be connected between constant voltage sources 1 and 2. In this case, R3 may also be set to 0 as shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, even if the threshold voltage of the transistor changes due to process variations, etc., the constant current source MO3F does not change the current flowing through the differential input circuit.
A bias circuit for ET can be provided. This makes it possible to create a differential input circuit whose frequency characteristics do not change even if there are process variations. Therefore,
Changes in characteristics of a larger scale circuit using this differential input circuit can also be eliminated, making it possible to optimally design a differential input circuit within an integrated circuit, and making it possible to create a high-performance integrated circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a circuit diagram when Fig. 1 is used in a differential input circuit, and Figs. 3 and 4 are circuit diagrams of other embodiments of the present invention. Circuit diagram: FIG. 5 is a circuit diagram of an example of a conventional gate bias circuit. 1... Constant voltage source (V'oo), 2... Constant voltage source (
Vss), 3...bias output terminal, Ml, M2...
・P-chMES FET, M3, M4---N-
ch MES FET, Mll, Ml2.15
．． Ml6・-P-chMO3FET, MlB, M4
, Ml7-N-chMO8FET, R, ~R3...resistance. Agent Patent Attorney Susumu Uchihara 4 octopus dishes

Claims (1)

[Claims] A first MESFET and a second MESFET each have the same conductivity and each substrate is connected to each source,
connected in series between a first constant voltage source and a second constant voltage source, and connected in series between the first constant voltage source and the second constant voltage source to the gate of each of these MESFETs. In the bias circuit configured by supplying a voltage divided by a plurality of resistors, the ratio W_1/L_1 of the channel length L_1 and the channel width W_1 of the first MESFET is
is substantially four times the ratio W_2/L_2 of the channel length L_2 and channel width W_2 of the second MESFET.