JPH0216646A - Programmable controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable controller that counts and stores the number of executions of a sequence program.

[Conventional technology]

Figure 6 is a system configuration diagram of a conventional programmable controller, in which (1) peripheral equipment with programming and monitoring functions, (2) ROM storing a program for executing sequence programs, (3) work RAM, (4) is a human power section that sends input signals to the calculation section;
(5) is a CPU (computation unit), and (8) is an output unit that outputs the computation results.

A conventional programmable controller is configured as described above, and monitors the calculation state and operating state of the CPII (5) by means of the peripheral device (1). For example, in Figure 7 (a
), the device MO is turned ON for one scan at the rise of the load xO, so the 7th
As shown in Figure (b), when the monitor timing is a%b, the state of the device MO is confirmed to be OFF.

[Problem to be solved by the invention]

Since conventional programmable controllers are configured as described above, there is a problem in that an instruction that is executed only once at startup is turned on and off at the monitor interval, making it difficult to confirm whether the instruction has been executed or not. there were.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a programmable controller that can store whether an instruction has been executed or not, as well as the number of times the instruction has been executed.

[Means to solve the problem]

The programmable controller according to the present invention stores in the memory of the programmable controller, counts the number of executions of an instruction for each step of a sequence program,
It is equipped with a counter area for storing information.

(Operation) By counting the number of times each instruction in a sequence program is executed, the programmable controller of the present invention can confirm whether or not an instruction has been executed, even if it is difficult to confirm whether or not the instruction has been executed.

(Example) Hereinafter, an example of the present invention will be described based on the drawings. In FIG. 1, (1) to (6) indicate the same parts as the conventional one shown in FIG. 6, and (7) is a counter area for storing the number of executions of a sequence program.

When monitoring the number of program executions, specify the range of the program whose execution number you want to check using the peripheral device (1), and communicate the memory contents of the specified range from the counter area (7) of the programmable controller main body. The data can be read into the peripheral device (1) through the device, and the results can be displayed on the CRT of the peripheral device.

The counter area (7) of the programmable controller configured as above has a counter for each step as shown in Figure 3, and when the output command of the sequence program is executed, the counter area (7) of the programmable controller configured as above has a counter for each step as shown in Figure 2. The value of the counter corresponding to is incremented by 1, and no processing is performed when it is not executed.

Therefore, even in the case of a program that executes only one scan at the rise of the load xO as shown in FIG. 7(a), it is possible to check whether the instruction has been executed by monitoring the counter area.

This will be further explained in detail based on Figure 4.5.
When executing a sequence program as shown in FIG. 7(a), the CPU (5) first executes the O step instruction LDXO.
Execute. At that time, the LD instruction shown in FIG. 5(b) is processed. In this case, the LDXO stores the contents of xO (see FIG. 5(a)) in a certain register of the CPU (5) (ON or OFF).
FF?) is written, so judge whether the content is ON or OFF (S1 in Figure 5(b)).If ON, set the 0 step flag to ON (S2 in Figure 5(b)). Add t to the counter content of the execution step (0 in this case) (
Figure 45 (b) 53). Then, since the instruction code indicates how many steps the instruction is, the number of steps is added to the current step and the process is returned.

Next, since the one-step instruction is PLS, as shown in Fig. 5 (C
) processes the PLS command. Note that the PLS instruction is an instruction that is executed only when the condition changes from OFF to ON. The PLS instruction compares changes in the current input conditions from the flag from the previous execution (which was OFF the first time). In this case, the content of the flag is OFF, and the current input condition is OFF.
Because of N (Fig. 5(c) S5), the flag changes from OFF to O.
Since the change is to N, the device MO is ON (S6 in FIG. 5(c)), and the counter of the execution step (O in this case) is incremented by 1 (S7 in FIG. 5(c)).

Next, like the LD instruction, the number of steps for the PLS instruction is written in the instruction code (PLS instruction is 3), so add that number of steps to the current step (3+1) and process. Return. Finally, when the END command is issued, the counter of the execution step (4 in this case) is incremented by 1, the step number is set to O, and the process is returned.

In this way, the CPU (51) determines whether the instruction has been executed.

〔Effect of the invention〕

As described above, according to the present invention, since a counter area is provided in the system, it is possible to easily confirm whether or not an instruction has been executed, even if it is difficult to confirm whether the instruction has been executed or not.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of a programmable controller showing an embodiment of the present invention, FIG. 2 is a flowchart of the counting operation in the above embodiment, FIG. 3 is a detailed diagram of the counter area, and FIGS. 4 and 5 ( a) to (d) are CPU
FIG. 6 is a conventional system configuration diagram, and FIGS. 7(a) and 7(b) are simple program examples and their timing charts. In the figure, (5) is the CPU and (7) is the counter area. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A programmable controller comprising a counter area in a memory of the programmable controller that counts and stores the number of executions of an instruction for each step of a sequence program.