JPH02168174A - Ic tester - Google Patents

Abstract

PURPOSE:To check an IC without being affected by the processing and transferring time of a CPU by providing a counter which generates an address of a memory storing informations of a timing signal and a decision circuit to judge that an output signal of said IC is changed. CONSTITUTION:A prototype oscillator 2 is activated to send a clock signal 2t to a counter 11, so that the counter 11 is started. A buffer data 10h is sent from a memory 10 to a strobe generator 9 by an address signal 11g output from the counter 11. The phase of the strobe is scanned. Then, when an error signal 8t judged by an FF8 is changed from NG to GO, a coincidence circuit 12 determines it as a coincidence by a data 1i predicting GO which is preliminarily set from a CPU 1, with outputting a stop signal 12j thereby to stop the counter 11. The strobe timing informations of the memory 10 by the address signal 11g at this time become a transmission time DELTAt. Then, data is read from the memory 10 into the CPU 1 via a read/write data signal 1k.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC tester for testing the electrical characteristics of an IC.

[Conventional technology]

FIG. 6 is a block diagram showing a conventional general IC tester. In the figure, 1 is a CPU that controls the entire circuit;
2 is an original oscillator, 3 is a clock generator that generates a timing signal for the output waveform, 4 is a formant that forms the output waveform, 5 is a driver that determines the amplitude of the output waveform,
6 is a comparator for comparing the voltage level of the test IC 17, 8 is a flip-flop for error determination, and 9 is a strobe generator that serves as a trigger for the flip-flop 8. Also, la, lb
is a data signal sent from the CPUI to the clock generator 3 and strobe generator 9, 5c is an input signal to IC6, 6d is an output signal from IC6, 9e is a strobe signal output from strobe generator 9,
8f is an error signal output from the flip-flop 8.

In addition, ■ of comparator 7. The symbol indicates the specified voltage level.

Further, FIG. 7 is a waveform diagram showing the output propagation time of IC6 in FIG. 6. Here, the figure (a) shows the input signal 5C
(b) is the waveform of the output signal 6d, (c) is the waveform of the output signal 6d.
and (d) shows the waveform of the strobe signal 9e.

In the figure, Δt is the propagation time of IC6, ■. , is the voltage regulation level, and T is the boundary time between a good product (hereinafter referred to as "GO") and a defective product (hereinafter referred to as rNGJ). In addition,
The figure (C) shows the voltage regulation level ■. This is a strobe signal when H or higher is set as "GO", and (d) in the figure shows the voltage regulation level V. , 1 or less is the strobe signal when rNGJ is defined as rNGJ.

Next, using Figures 6 and 7, we will calculate the output propagation time Δ of the IC.
The operation when performing an AC characteristic test to test t will be explained. First, the data signal la sent from the CPUI
The clock generator 3 generates a clock signal based on. And Formattuta 4. Input signal 5C is output to IC6 via driver 5. After that, IC6
The output signal 6d outputted from the comparator 7 is set to the voltage regulation level V. 8 and outputs the result to flip-flop 8. At this time, the timing at which the flip-flop 8 determines the output signal 6d is determined by the strobe signal 9e generated by the strobe generator 9 based on the data signal 1b sent from the CPU 1. Here, when the strobe signal 9e has the waveform shown in FIG. 7(C), the error signal 8 output from the flip-flop 8
f becomes the rGOJ signal and is sent to the CPUI. Also,
When the strobe signal 9e has the waveform shown in FIG. 3(d), the error signal 8f becomes an rNGJ signal.

[Problem to be solved by the invention]

In this way, conventional IC testers only have a one-point measurement function, so they cannot be easily measured. When testing by measuring the absolute value of Δ for 1 hour, etc., the phase of the strobe signal 9e is changed while always sending data 1b from the CPU l to the strobe generator 9, and the CPU inputs the "GO" button while reading the error signal 8r. The task was to search for the boundary (symbol T) between and rNGJ. For this reason, there was a drawback that the CPU processing time and transfer time increased, and the test time became slower.

The present invention was made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide an IC tester that can test the AC characteristics of an IC without being affected by the processing time and transfer time of CPLII.

[Means to solve the problem]

An IC tester according to the present invention includes a memory that stores timing signal information for determination, a counter that generates an address for this memory, and a coincidence circuit that determines that an output signal of an IC has changed. .

[For production]

scan the phase of the generator timing signal by sending data from memory to the generator by a counter;
- Judgment of the output signal in the IC is performed using several circuits.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a high speed timing search logic tester showing an embodiment of the invention. In the figure, the sixth
The same parts as in the figures are given the same reference numerals.

6b is an output signal from IC6, IO is a memory with strophe timing information, 11 is a counter that generates an address for memory IO in synchronization with the cycle from the original oscillator 2, 12 is an output signal from rGOJ [NGJ, from rNGJ] G
This is a coincidence circuit 15 (EXOR circuit) that detects the boundary of "O". Also, li is the expected data output from cPUI,
lk is a read/write data signal between the CPU Ul and the memory 10, 2 is the clock signal of the counter 11 from the original oscillator 2, 10h is the sofa data output from the memory 10, and l1g is the address output from the counter 11. The signal 12j is a counter stop signal output from the matching circuit 12.

FIG. 2 is an explanatory diagram showing the operation of the memory IO in FIG. 1. Here, the memory IO stores data from address 0 to address N.

FIG. 3 is a waveform diagram showing the output propagation time of IC6 in FIG. 1. Here, (a) in the same figure shows the waveform of the human input signal 5c, (b) in the same figure shows the waveform of the output signal 6b, and (c) in the same figure shows the waveform of the strobe signal 9e. In the figure, the propagation time of 6 ports and IC6 is shown.

FIG. 4 is a waveform diagram showing the boundary time T between rGOJ and rNGJ. The figure (a) shows the waveform of the output signal 6b, the figure (a) shows the waveform of the output signal 6b;
b) shows the waveform of the strobe signal 9e.

In the above configuration, the operation of the IC tester will be explained according to the flowchart shown in FIG. First, the transmission time Δt can be measured by determining the strobe timing at the boundary from "NG" to rGOJ. For this reason, strobe timing information indicating the phase of the strobe operation is written from the cput to the memory IO via the read/write data signal 1k as shown in FIG. 2 (step 11). Next, the original oscillator 2 is activated and the clock signal 2t is sent to the counter II to start the counter 11 (step 12). And Counter II
In response to the address signal 11g generated from the address signal 11g, the memory 10 sends phase data loh to the strobe generator 9, and the phase of the strobe is scanned as shown in FIG. 4(b) (step 13). Next, flimp frond 8
It is determined whether or not the error signal 8d determined in step 4 changes from rNGJ to rGOJ as shown in FIG. 4(a).
Step 14), if there is no change from rNGJ to rGOJ, continue the star lobe scan; if there is a change from rNGJ to rGOJ, the coincidence circuit 12
It is determined that there is a match, the stomp signal 12j is output and the counter 11 is stopped (step 15), and
The strobe timing information of the memory 10 using the address signal 11g at that time becomes the propagation time Δ[. that time,
While scanning the strobe, the clock generator 3. Stroopgelator 9. counter 1
The clock signal 2f to 1 is the counter stop signal 12
It is assumed that the output is repeated until j appears. Thereafter, data is read from the memory 10 to the CPU via the read/write data signal 1k (step 16).
).

In this way, the IC tester in this embodiment has a simple circuit configuration that just adds circuits such as a memory and a counter to the strobe generator circuit, and can perform high-speed propagation time measurements without performing processing via a conventional CPU. AC characteristics tests can be performed.

In the above embodiment, the test of the output propagation time of an IC was explained, but by reusing this function, it can be used for high-speed processing such as an IC analysis function in an IC tester (for example, a shmu program, a logic analyzer, etc.). It can be applied and produces the same effects as the above embodiments.

[Effects of the Invention] As described above, the present invention scans the phase of timing No. 13 of the generator by sending data from the memory to the generator using a counter, and determines the output signal in the IC using a -number circuit. CP as before.
The test can be performed without going through the U process. This allows processing and transfer times to be extremely short.
AC characteristics tests such as high-speed propagation time measurements can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a high-speed timing search loss tester showing one embodiment of the present invention, and FIG. 2 is a block diagram of a memory 1
Figure 3 is a waveform diagram showing the output propagation time of IC6, Figure 4 is a waveform diagram showing the boundary time T between rGOJ and rNGJ, and Figure 5 shows the operation of the IC tester. 6 is a block diagram showing a conventional general IC tester, and FIG. 7 is a waveform diagram showing the output propagation time of IC 6 in FIG. 6. 1...CPU, 2...IC, 10...Memory, 1
1...Counter, 12...-number circuit.

Claims (1)

[Claims] An IC tester having a generator that generates a timing signal for determining an output signal of an IC, comprising: a memory storing information on the timing signal for determining the IC; a counter generating an address for the memory; , and a coincidence circuit that determines that the output signal of the IC has changed.