JPH02168641A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for dividing a semiconductor chip that has undergone a predetermined process into individual chips and selecting only good chips. The present invention relates to a marking method that facilitates the selection.

[Conventional technology]

In the conventional manufacturing process of semiconductor devices, a plurality of semiconductor chips (hereinafter simply referred to as chips) are formed on a semiconductor wafer (hereinafter simply referred to as wafer) that has undergone a predetermined process.
The wafer test process includes a step of measuring whether the wafer has desired electrical characteristics and determining its acceptability (this step is usually called a wafer test step). In this wafer testing process, technology to measure electrical characteristics and determine pass/fail is of course important, but pass/fail judgment marks are placed on each chip (including semiconductor devices inside). How to apply it to one object is also one of the important techniques. Hitherto, as this marking method, a marking method using ink adhesion has been most commonly used as a well-known technique.

FIG. 3 is a schematic diagram showing the conventional marking method using ink adhesion. In this figure, 1 is a probe card corresponding to the wafer to be measured, 2 is a measurement probe, 3 is a marker (also called an inker) for attaching ink to the chip for discrimination, 4 is a wafer, and 5 is a marker for attaching ink to the chip. 1 is a mounting table for the wafer 4, and 6 is a control device that measures the electrical characteristics of the wafer 4 and determines its quality.

FIGS. 4(a) and 4(b) are configuration diagrams showing an example of the operation of the marker 3 shown in FIG. 3, respectively. The components of the marker 3 include an ink reservoir 31, a marker needle 32, and an electromagnet 34.
, iron piece portion 35 and ink 36. Note that 33 is a fulcrum.

Next, a conventional marking method using ink adhesion will be explained using FIG. 3 and FIGS. 4(a) and (b).

First, the wafer 4 that has undergone a predetermined unifly process is placed on the mounting table 5.
Place it on top. At this time, the wafer 4 is normally positioned (aligned) in three directions, ie, the horizontal direction, the vertical direction, and the rotational direction, in correspondence with the probe card 1 . In the measurement, first, the probe 2 and the probe card 1 are arranged opposite to the wafer 4 so that the electrical properties of the chip on the desired wafer 4 can be measured and judged, and the electrical properties of the wafer 4 are measured. The control device 6 is set to determine. Next, the probe 2 is brought into contact with a predetermined electrode portion (not shown) on the wafer 4, and the control device 6 applies an electric signal for measurement to the wafer 4 through the probe card 1 and the probe 2.

Thereafter, the measurement results are transmitted to the control device 6 through the probe 2 and the probe card 1. In response to this, the control device 6 compares it with a predetermined program to determine the quality of the chip. Here, an electrical signal to apply ink is transmitted to the marker 3, and in response to this, ink is deposited on the chips of the wafer 4.

Next, the operation of the marker 3 will be explained in detail based on FIGS. 4(a) and 4(b).

Normally, when there is no electrical signal to inject ink, the marker 3 is in a state as shown in FIG. 4(a). That is, the tip of the marker needle 32, which is the main part of the marker 3, is completely contained in the ink 36 in the ink reservoir 31. Here, when an electric signal to inject ink is transmitted to the 'rL magnet 34, the electromagnet 34 is magnetized in accordance with the signal, and the iron piece 35 is thereby attracted. Iron piece part 3
5 is attracted, the marker 3 rotates about its fulcrum 33 in the direction of the arrow as shown in FIG. 4(b), and the tip of the marker needle 32 comes out of the ink reservoir 31. the result,
The ink 36 adhering to the tip of the marker needle 32 adheres to a predetermined chip on the wafer 4.

The above is an overview of the marking method using ink adhesion, but in reality, in order to measure all the chips fabricated in large quantities on the wafer 4 and judge their acceptability, measurements are taken according to the size of the chips that make up the semiconductor device. A mechanism for regularly moving the mounting table 5 vertically, horizontally, and vertically may be provided, or the timing for depositing ink may be changed during measurement (i.e., when the probe 2 contacts the wafer 4 and the measurement signal, etc. Instead of determining the defect (when electrical signals are exchanged based on the control device 6), once the electrical signal to inject ink is memorized, several chips are marked with ink at once. Improvements have been made to do this. However, the mechanism for depositing the ink 36 is roughly as shown in FIGS. 4(a) and (b). That is, an electric signal for attaching the ink 36 is transmitted to the electromagnet 34, and the electromagnet 34 is magnetized by this signal to move the tip of the marker needle 32, and the ink 36 attached to the tip is attached to the chip. It is something that makes you Next, when the electric signal to ink is gone, the electromagnet 3
4 is no longer magnetized, the iron piece 35 separates from the electromagnet 34. For example, a spring (not shown) is usually used for this restoration.

Normally, a large number of semiconductor devices are formed on the wafer 4 at the same time, and the processing time for the chips including these semiconductor devices (i.e., for example, by moving the mounting table 5, bringing the probe 2 into contact with the wafer 4, and applying various electrical Regarding the time required to measure characteristics, judge the quality of the results, and mark defective products for identification, the individual processing times must be short in consideration of mass production. Therefore, the time for applying the ink 36 must be as short as possible and must be performed reliably. Further, the shape of the ink 36 deposited on the wafer 4 must always be of an appropriate size compared to the shape of the chip. For example, if the shape of the ink 36 is too large and becomes larger than the chip size, the ink 36 will adhere to good chips as well, causing good chips to be mistaken as defective. Moreover, if the shape of the ink 36 is too small, it will be difficult to determine whether it is a defective product. Therefore, a great deal of attention and effort is required to adjust the shape of the ink to an appropriate size.

Although it has the drawbacks as mentioned above, there is no practical alternative, so the marking method using ink adhesion is
It is used in the test process of many wafers 4, especially in the test process for wafers that do not require a special process after the process, that is, the test process for wafers for which the process has been completed.

However, due to restrictions on wafer testing, models that require a wafer test even after the wafer test, ie, models that require the wafer test to be performed during the wafer test, are being put into practical use in recent years.

As an example, among FETs (field effect transistors) formed on GaAs (gallium arsenide) wafers,
In particular, there are transistors for high output.

The most commonly used high-output transistors to date are flip-chip transistors.
There is something called ip type). A cross-sectional view showing the concept of this flip-chip type GaAsFET is shown in FIG.

In this figure, a source electrode 22 and a drain electrode 23 are formed on a GaAs wafer 21, and a gate electrode 22 is formed in an intermediate region between the two (usually referred to as a channel region).
4 is formed.

The most well-known structure of GaAs is FET (commonly known as MESFET), in which the GaAs wafer 21 and the source electrode 22 and drain electrode 23 make ohmic contact, and the GaAs wafer 21 and the gate electrode 24 make Schottky contact.
It is an sFET. In order to stably flow a large amount of current and to enhance the heat radiation effect, this source electrode 22. The gold-plated portion 25 serves as an electrode for drawing the drain electrode 23 to the outside.
and 26 are formed. However, the gate electrode 24
Similarly, a lead electrode to the outside is formed for the gate electrode 24, but since this gold-plated part is usually formed on the gate electrode 24 extending outside the channel region, in FIG.
Not shown. Of course, in a normal high-power transistor, there are multiple source parts (source electrode and its gold-plated part), drain parts (drain electrode and its gold-plated part), and gate parts (gate electrode and its gold-plated part) on one chip. is formed, but only its basic unit is shown in FIG.

On the other hand, the thickness (1) of the GaAs wafer 21 is approximately 5QO1.Lm at the beginning of the sea urchin fly process, but is approximately 200 μm at the end of the sea urchin fly process (i.e., the state shown in FIG. 5).
It has been shaved to a certain extent. In comparison, the thickness of the gold plated portions 25 and 26 is approximately 10 μm, and the thickness of the gold plated portions 25 and 26 is approximately 10 μm. The thicknesses of the drain electrode 23 and the gate electrode 24 are all 1 μm or less.

For the squares formed in the state shown in FIG. 5, it is possible to measure electrical characteristics and apply marks based on the results using the method described in detail in the ink adhesion method described above.

In addition, after the mark is attached after the pass/fail judgment, a well-known chip dividing method is used, for example, a diamond scriber is used to draw marks on the surface according to the size of the chip, and then some external force is applied to separate the chips into individual chips. All you have to do is divide it into chips and assemble only good chips that are not marked. At this time, defective chips can be easily identified by ink adhesion.

Furthermore, it is well known that by performing an external appearance inspection of the chips, if necessary, it is possible to contribute to improving the yield after assembly.

In the flip-chip type described above, the wafer test process is completed before the wafer test process, and the wafer thickness is approximately 200 μm, so the above-mentioned electrical property measurement and marking method using ink adhesion can be applied. It is.

As a type different from the flip-chip type described above, a type called a via hole type (Via Hole type) has been put into practical use. A cross-sectional view showing the concept of this via-hole type GaAsFET is shown in FIG.

In this figure, a source voltage 8 is placed on the GaAs wafer 21.
i22 and a drain electrode 23 are formed, and a gate electrode 24 is formed in an intermediate region (channel region) between the two. The GaAs wafer 21, the source electrode ti22 and the drain electrode 23 make ohmic contact, and the GaAs
The FET (commonly known as MESFET) has a Schottky contact structure between the wafer 21 and the gate electrode 24, which is the same as a flip-chip FET. In order to stably flow a large amount of current and to enhance the heat dissipation effect, the source electrode 22. Gold-plated parts 25 and 26 are formed as electrodes for leading the drain electrode 23 to the outside in the same way as in the case of FIG. 5, and although not shown, the gate electrode 24
A gold-plated portion is similarly formed on the gate electrode 24 as an electrode for leading to the outside. In Figure 6,
Although only the basic unit is shown, in reality, a plurality of source, drain, and gate parts are formed on one chip. In addition, in the portions corresponding to the source electrode 22 and drain electrode 23, holes (referred to as via holes) are formed that penetrate from the back surface of the wafer to the source electrode 22 and drain electrode 23 on the front surface, respectively. It is completely filled with gold plating. In other words, the source gold plated portion 27. is embedded in the via hole penetrating the source electrode 22. A drain gold-plated portion 28 is formed embedded in a via hole penetrating the drain electrode 23.

The thickness (1) of the GaAs wafer 21 is about 30 μm after the final wafer, that is, in the state shown in FIG. In comparison, the thickness of the gold-plated portion 25°26 is approximately 5 μm.
The thickness of the source electrode 22, drain electrode 8i23, and gate electrode 24 are all 1 μm or less.

In this pie-hole type FET, it is very important to control the thickness (1) of the GaAs wafer 21 and the overall thickness including the gold-plated portion. That is, when forming the pie holes corresponding to the source electrode 22 and the drain electrode Vi23 by etching from the back surface, Ga
If the thickness (1) of the As wafer 21 varies within the wafer, the shape of the via hole will not be constant, and if the via hole is small, there will be sufficient distance from the source electrode 22 and drain electrode 23. It becomes impossible to extract current, and the discharge effect deteriorates. On the other hand, if the hole in the pie hole is large, in extreme cases,
Source electrode 22. If the drain hole protrudes from &23, the wafer will be defective.

Due to the above constraints, measuring the electrical characteristics of the chip and marking its pass/fail using the conventional ink deposition method makes it difficult to keep the shape of the deposited ink (ink size and thickness) uniform. However, since it is not realistically possible, we have no choice but to adapt. Therefore, for this pie-hole type GaAsFET, a method of scratching the gold-plated portion, for example, is applied as an alternative to marking by ink adhesion.

An outline of this method will be explained below.

In FIG. 4(a), a marker 3 is prepared from which only the ink reservoir 31 and ink 36 are removed. Note that the other conditions are the same as the marking method using ink adhesion described in detail. If the electrical characteristics are determined to be defective as a result of the measurement, a signal that magnetizes the electromagnet 34 (that is, a signal that corresponds to a "signal to apply ink" in the marking method using ink adhesion) is sent to the electromagnet 34. The iron piece 35 is thereby attracted. When the iron piece 35 is attracted, the marker 3 moves to its fulcrum 3.
3 in the direction of the arrow, the tip of the marker needle 32 approaches the surface of the wafer 4.

If the stroke (traveling distance) of the marker needle 32 is appropriately controlled, the tip of the marker needle 32 can reach the top of the wafer 4, and this tip can be connected to the source electrode 2.
2 or the gold-plated portion 25 of the drain electrode 23. Alternatively, by controlling the contact point 26, it is possible to attach defective marks (scratches) to the surface of the chip.

(Problems to be Solved by the Invention) As mentioned above, the ink can be applied to the wafer 4 to which the marking method by ink adhesion can be applied, and the size of the ink is appropriate compared to the shape of the chip, and the ink can be applied in a short time. If the shape of the ink is too large and becomes larger than the chip size, there is a drawback that the ink will adhere to good chips as well, causing them to be mistaken as defective chips. Furthermore, if the shape of the ink is too small, there is a drawback that it becomes difficult to determine whether the ink is good or bad. However, adjusting the shape of the ink to an appropriate size required a great deal of attention and effort.

Further, for the wafer 4 to which the marking method by ink adhesion cannot be applied, for example, a method of scratching the marking part is applied, but the mark caused by this scratch necessarily needs to be small. After dividing into individual chips, if you use this mark as a guide to select good chips, you cannot easily identify them without using a microscope. In addition, when the wafer is thin, it is vulnerable to impact and has problems such as difficulty in wafer testing and marking.

This invention was made to solve the above-mentioned conventional problems, and it is possible to mark defective products using ink or the like on any semiconductor wafer, and to clearly mark the defective products. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reliably provide a judgment mark.

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention measures the electrical characteristics of a chip formed on a semiconductor wafer to determine whether the chip is good or bad, and based on this determination result, the semiconductor device is defective. a first marking step of applying a fine first mark to the chip;
The method includes a second marking step of applying a second mark that is easier to identify than the first mark to the front or back surface of the defective chip based on the first mark applied in the first marking step.

[Effect]

In this invention, a minute first mark is given to a defective chip to which a marking method of attaching ink cannot be applied due to process constraints, and an ink is attached based on this first mark to make it larger. Since the second mark is provided on the front or back side, the mark for determining pass/fail is appropriately sized and clearly displayed, making it easy to distinguish between good and bad.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to (e) are diagrams for explaining one embodiment of the present invention, and FIG. 1(a) is a diagram for measuring the electrical characteristics of a chip formed on a GaAs wafer 11 and detecting defects. FIG. 3 is a top view showing a state in which fine first marks 13 are provided on the chip. In this case, the mark (referred to as the first mark) 13 is
For example, it means a scratch made by the tip of the marker needle 32 mentioned above.

FIG. 1(b) shows that after the state shown in FIG. 1(a), the GaAs wafer 11, which has undergone the desired pie-hole forming process, is pasted so that the back surface of the wafer is in contact with the glass disk 12 (the pasting method is, for example, A second mark 14 is shown on the chip surface corresponding to the first mark 13 formed on the chip (by a well-known method such as a wax method). Regarding the determination of the presence or absence of the first mark 13, for example, the chip state may be projected on a television image and the determination may be made by a human being, or by applying the latest pattern recognition technology, the chip state may be automatically determined. It is also possible to determine the presence or absence of the mark 13 of No. 1. Further, the second mark 14 may be applied by using the above-mentioned ink adhesion method, or is not necessarily limited to this method as long as it provides a clear mark.

FIG. 1(C) is a sectional view taken along line AA' in FIG. 1(b).

From FIG. 1(b) onwards, the entire GaAs wafer 11 is divided by a well-known chip dividing method, for example, by marking the surface according to the chip size using a diamond scriber, and then by melting wax, for example. is removed from the glass disk 12 and divided into individual chips. Thereafter, after cleaning and drying the chips, only good chips with no marks attached are selected and assembled. In this case, since the second mark 14 is clearly attached to the defective chip, it is possible to easily determine whether the chip is good or bad. (At this time, it is well known that if necessary, further visual inspection of the chip can contribute to improving the yield after assembly.) FIG. 2(a) is a diagram for explaining an example, and FIG. 2(a) is a diagram of a state in which the electrical characteristics of a chip formed on a GaAs wafer 11 have been measured and a first defective mark 13 has been added, as seen from the back side. be. The first mark 13 in this case means, for example, a scratch made with the tip of the marker needle described above.

FIG. 2(b) shows that after the state shown in FIG. 2(a), the GaAs wafer 11, which has undergone the desired hole-forming process, is pasted so that the wafer surface is in contact with the glass disk 12 (the pasting method is A second mark 14, which is easier to identify than the first mark 13, is provided on the back surface of the chip in correspondence with the first mark 13 formed on the chip (by a well-known method such as a wax method). It is a figure showing a state. Regarding the determination of the presence or absence of the first mark 13, for example, the state of the chip surface observed through the glass disk 72 may be projected onto a television image, and the determination may be made by a human based on that. Alternatively, the latest pattern recognition technology may be used. If applied, it is also possible to automatically determine the presence or absence of the first mark 13. Further, the second mark 14 may be applied by using the above-mentioned ink adhesion method, or is not necessarily limited to this method as long as it provides a clear mark. Furthermore, FIG. 2(b) shows a method (G
This example shows an example of the etch-cut method in which grooves are formed on the aAs wafer 11 using etching, in which grooves are first formed from the front surface of the wafer, and then grooves are formed from the back surface of the wafer. A groove is formed at the location, and a groove that finally penetrates is formed. Therefore, the GaAs wafer 11 to which this method is applied is attached to the glass disk 12 with wax in a state in which the individual chips are aligned. Glass disk 12 used at this time
Since the chip surface is observed through the wax, it is desirable that the wax be transparent.

FIG. 2(c) is a sectional view taken along line AA' in FIG. 2(a).

From Figure 2 (C) onwards, by melting the wax,
The entire aAs wafer 11 is removed from the glass disk 12 and divided into individual chips. After that, after washing and drying the chip, the first step. It is only necessary to select and assemble only good chips to which the second marks 13 and 14 are not attached. In this case, since the second mark 14 is clearly provided on the defective chip, it is possible to easily determine whether the chip is good or bad. (At this time, if the appearance of the chip is inspected, it can contribute to improving the yield after assembly, as in the above example.) In addition, although each of the above embodiments has been explained based on a GaAsFET, this invention It is not limited to this.

Further, the method of applying the mark is not limited to the method shown in the embodiment.

〔Effect of the invention〕

As explained above, this invention measures the electrical characteristics of chips formed on a semiconductor wafer to determine whether they are good or bad, and based on the results of this determination, fine first
a first marking step for applying a mark; and a second mark that is easier to identify than the first mark on the front or back surface of the defective chip based on the first mark applied in the first marking step. Since the second marking process includes a second marking step for applying a mark, it is possible to apply a clear defect mark to a defective chip. As a result, when divided into individual chips, it is easy to determine whether the chips are good or bad.
This has the effect of improving workability after dividing into chips.

Furthermore, the process of observing the first mark and determining whether the chip is good or bad based on the first mark can be automated by using well-known pattern recognition technology. Since the chips are aligned, the marking method can also be easily automated by using a well-known technique (for example, the above-mentioned marking method using ink adhesion).

In addition, if a second marking method is adopted, for example, applying ink made by dissolving a magnetic material such as iron powder in a solvent such as oil, only the defective chips to which this ink has adhered can be marked using a magnet. It is also possible to remove it.

As described above, according to the present invention, it is possible to reliably mark defective chips by only making slight changes to the conventional apparatus.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram illustrating a marking method according to an embodiment of the present invention, FIG. 2 is a schematic diagram illustrating a marking method according to another embodiment of the invention, and FIG. 3 is a wafer test process and marking process. A schematic configuration diagram showing the method, FIG. 4 is a configuration diagram for explaining the marking operation of FIG. 3,
Figure 5 is a cross-sectional view schematically showing a flip-chip type GaAs MESFET, and Figure 6 is a pie-hole type GaAs MESFET.
FIG. 2 is a cross-sectional view schematically showing an FET. In the figure, 1 is a probe card, 2 is a measurement probe,
3 is a marker, 4 is a semiconductor wafer, 5 is a mounting table, 6 is a control device, 11 is a GaAs wafer, 12 is a glass disk, 13
is the first mark, and 14 is the second mark. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure: Plow 7 Card 6: Control equipment diagram Procedure amendment (voluntary) ・1. ' Heisei 2 Character j 惺Se 廿 Year Month Day 1, Indication of the case Patent Application No. 1983-324232 Name of the invention Method for manufacturing semiconductor devices 3, Person making the amendment Relationship to the case Patent applicant address Chiyoda-ku, Tokyo 2-2-3 Marunouchi Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, Agent address Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (7375) Patent attorney Masuo Oiwa (Contact number 03 (213) 3421 Licensing Department) ・Naimu 2/
5. Column 6, Detailed explanation of the invention in the specification to be amended, Contents of the amendment (1) On page 4, line 8 of the specification [Here, ink is replaced with ``J is determined to be defective.'' If it does, please ink it.'' (2) Similarly, "discharge" on page 13, line 6 is corrected to "heat radiation." (3) Also commonly referred to as Type 1 on page 20, line 18)
is corrected as ``formula''. that's all

Claims (1)

[Claims] a first marking step of measuring the electrical characteristics of the chips formed on the semiconductor wafer to determine whether they are good or bad, and applying a fine first mark to the defective chips based on the determination results; The method further includes a second marking step of adding a second mark that is easier to identify than the first mark to the front or back surface of the defective chip based on the first mark provided in the first marking step. A method for manufacturing a featured semiconductor device.