JPH021698A - Charge storage type photoelectric conversion device - Google Patents

Abstract

PURPOSE:To obtain the output of good S/N by switching and controlling the charge storage mode of photoelectric conversion element train by a charge storage control part. CONSTITUTION:The title device is provided with the photoelectric conversion element trains 1a to 1c capable of operating in the different charge storage modes and the charge storage control parts 2a to 2c to control the charge storage operation of every element train and the charge storage mode of the element trains 1a to 1c is switched and controlled under the control of the control parts 2a to 2c. At the time of low luminance, when the device is controlled so that charge storage is performed by light receiving element trains PDa to PDc of less generation of a dark time charge, and the stored charge is held in charge storage element trains STa to STc, the influence of the dark time charge can be reduced. At the time of high luminance, when the device is controlled so that the charge storage is performed by the element trains STa to STc of smaller areas than the element trains PDa to PDc, and the stoted charge is held by the element trains STa to STc, the read-out time of the stored charge can be shortened. Thus, the output of good S/N can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a charge accumulation type photoelectric conversion device; it is particularly suitable as a focus detection element of an autofocus camera having a plurality of focus detection areas. .

[Prior Art] Conventionally, it has been proposed to use a charge accumulation type photoelectric conversion element such as a COD line sensor as a focus detection element of a camera. A COD line sensor consists of a light-receiving element array, a charge storage element array that accumulates charges obtained from the light-receiving element array, and a charge transfer element that transfers the accumulated charges in the charge storage element array in parallel and reads them out in series according to a lock. It is extremely suitable as a focus detection element because it can detect an n-variant distribution on a line in which light-receiving element arrays are arranged, and can read out luminance distribution data in a self-scanning manner. However, the CCD line sensor does not detect the absolute amount of light received, but rather detects the brightness distribution of the light irradiated onto the light receiving element array by looking at the relative value of the charge accumulated in the charge storage element array. We have come to know that if the received light is too strong, the output from the charge storage element array will be saturated and the output signal will be distorted, and if the received light is too weak, the output from the charge storage element array will be low. Therefore, there is a problem that the S/N ratio deteriorates. Therefore, a light-receiving element for brightness monitoring is arranged near the light-receiving element row, more preferably between each light-receiving element, and the charge accumulation time in the charge storage element row is controlled according to the brightness monitor output. It has been proposed to control the charge accumulation amount to an appropriate value by shortening the charge accumulation time when the luminance is high and increasing the charge accumulation time when the luminance is low.

In addition, Japanese Patent Application Laid-open No. 60-256279 discloses that for a one-line CCD line sensor, the light-receiving element array is divided into a plurality of blocks, a light amount monitor is placed in each block, and the charge accumulation time is controlled for the brightest block. However, the blocks are not arranged discretely, but are arranged close to each other on one line, and the difference in light amount between the blocks is not very large. Further, the control method for charge accumulation time is not switched depending on the amount of light.

[Problems to be Solved by the Invention] Incidentally, in an autofocus camera having a plurality of focus detection areas, it is necessary to discretely arrange a plurality of CCD line sensors. In this case, since different objects are captured in each focus detection area, the object images formed on each CCD line sensor are also different, and the brightness thereof is also different. Therefore, if the charge accumulation time of each CCD line sensor is controlled according to the average brightness of the entire screen, the charge accumulation time may be too long than the appropriate value and the output will be saturated, or it may be too short and the S/N ratio will be reduced. There were times when it decreased. As described above, when the output of the CCD line sensor becomes saturated or the S/N ratio decreases, there is a problem in that accurate automatic focus detection becomes impossible, resulting in incorrect focus detection.

The present invention has been made in view of these points, and its purpose is to reduce the charge M of a plurality of photoelectric conversion element arrays.
It is an object of the present invention to provide a charge storage type photoelectric conversion device in which a product operation can be appropriately controlled.

[Means for Solving the Problems] In order to solve the above problems, the charge storage type photoelectric conversion device according to the present invention has a charge storage type photoelectric conversion device that can operate in different charge storage modes, as shown in FIG. Multiple photoelectric conversion element rows 1
a to 1c, and charge accumulation control units 2a to 2c that control the charge accumulation operation of each photoelectric conversion element array 18 to 1c, and each photoelectric conversion element array 1a to 1c includes a charge accumulation control unit 2a to 2c.
It is characterized in that the charge accumulation mode is switched and controlled under the control of.

Here, the charge accumulation mode is preferably switched based on the amount of light incident on the photoelectric conversion element arrays 1a to 1c or the length of the charge accumulation time. If a hysteresis characteristic is provided for switching this charge accumulation mode, in other words, the switching from the high-luminance charge accumulation mode to the low-luminance charge accumulation mode will By setting the brightness at which the charge accumulation mode is switched to a low value, the frequency of switching the charge accumulation mode can be reduced.

In addition, the charge accumulation mode for low brightness is
A to 1c are controlled by the same charge accumulation time, and the charge accumulation mode for high brightness is controlled by each photoelectric conversion element array 1a to 1c.
It is preferable to adopt a mode in which each of the charge accumulation times 1c is controlled by a separate charge accumulation time.

Furthermore, in the charge accumulation mode for low luminance, charge is accumulated in the light receiving element arrays PDa to PDc in the photoelectric conversion element arrays 18 to 1c, and the accumulated charges are held in the charge storage element arrays STa to STc, and the charges for high luminance are stored. In the record storage mode, it is preferable that charges are accumulated in the charge storage element arrays STa to STc and the accumulated charges are held in the charge storage element arrays STa to STc.

Operation] In the charge accumulation type photoelectric conversion device of the present invention, the operation when controlling the charge accumulation mode to be switched according to the amount of incident light will be described.

First, when the amount of incident light is large (at high brightness),
Since the charge accumulation time is relatively short and the influence of dark charges during charge accumulation operation is small, each photoelectric conversion element array 1a to 1
The charge accumulation time of c is controlled to be a long time within a limit that does not saturate the output, and at a time corresponding to the amount of incident light.6 The photoelectric conversion device of the present invention includes photoelectric conversion element arrays 18 to
Luminance distribution of the part where 1c is provided? Since the detection is performed relatively, the S/N ratio can be improved by setting the charge accumulation time to be long within the limit where the output is not saturated, and the brightness distribution data can be detected accurately. The stored charge is read out after the charge accumulation operation of all the photoelectric conversion element rows is completed, and the photoelectric conversion element row that finished the charge storage operation first is read out until the charge storage operation of the other photoelectric conversion element rows is completed. Although it is on standby, the charge storage time is relatively short at high brightness, so there is little risk that the S/N ratio will deteriorate due to dark charge accumulated during standby. STc is the photodetector array PDa to PD
By making the area smaller than c and setting the potential while holding the accumulated charges high, it is possible to reduce the generation of dark charges during standby.

On the other hand, when the amount of incident light is small (low brightness),
Since the charge accumulation time is relatively long and the influence of dark charges during the charge accumulation operation is large, each photoelectric conversion element array 1a
~1c are controlled with the same charge accumulation time. In other words, 1
When one photoelectric conversion element array finishes its charge accumulation operation, the other photoelectric conversion element arrays also finish their charge accumulation operation at the same time.
Alternatively, when a predetermined period of time has elapsed without any of the photoelectric conversion element arrays completing their charge accumulation operations, all of the photoelectric conversion element arrays complete their charge accumulation operations. Therefore, the photoelectric conversion element array that has completed its charge accumulation operation first does not need to wait until the charge accumulation operation of the other photoelectric conversion element arrays has been completed.
In this state, a gain corresponding to the amount of incident light is supplied to each photoelectric conversion element array, so that the S/N ratio does not deteriorate due to dark charges accumulated during standby.

In addition, at low brightness, the influence of dark charges can be reduced by controlling the charge accumulation in the photodetector arrays PDa to PDc, where less charge is generated in the dark, and holding the accumulated charges in the charge storage element arrays STa to STc. At high brightness, the charge storage element arrays STa to STc, which have a smaller area than the light receiving element arrays PDa to PDC, perform charge storage, and control is performed so that the accumulated charges are held in the charge storage element arrays STa to STc. For example, the readout time of accumulated charges can be shortened.

More detailed structure and operation of the present invention will be explained in detail in the following description of the embodiments.

[Example] Second example about the optical system for focus detection in a single-lens reflex camera with an automatic focus detection function using the photoelectric conversion device of the present invention
This will be explained with reference to the drawings and FIG. - The camera body of the eye reflex camera is provided with a photographing lens 11 on the optical axis 1o, a main mirror 12 is provided at an upward angle of 45 degrees behind the photographic lens 11, and a film exposure surface 13 is provided behind the main mirror 12. A photographing light beam passing through a photographing lens 11 is reflected upward by a main mirror 12, formed into an image by a focus plate, and guided to a finder optical system via a pentaprism.

At least a part of the main mirror 12 is formed into a half mirror, and a rotation shaft is pivotally attached to the back surface of the main mirror 12 between the half mirror part of the main mirror 12 and the film exposure surface 13. A secondary mirror 14 is provided downward at 45 degrees,
The focus detection light flux that has passed through a part of the half mirror of the main mirror 12 is reflected downward by the sub mirror 14 and guided to a focus detection device 15 disposed at the bottom of the mirror box of the camera body.

During photography, the main mirror 12 and the secondary mirror 14 are rotated forward and upward to retreat from above the optical axis 10, and the photographing light flux that has passed through the photographic lens 11 forms an image on the film exposure surface 13.
This provides imagewise exposure to the exposed film surface 13.

- The focus detection device 15 includes three photoelectric conversion element rows 1.
An AP sensor 17 comprising 6a, 16b and 16c is provided. Among the photoelectric conversion element rows 1.6a to 16c,
One photoelectric conversion element row 16a is arranged at a horizontal position that includes the optical axis 10, and two photoelectric conversion element rows 16b and 16c are arranged at vertical positions that do not include the optical axis 10 on both sides of the photoelectric conversion element row 16a. It is located in Photoelectric conversion element array 16b, 1
6c is oriented at approximately 90 degrees with respect to the photoelectric conversion element array 16a.

In front of the AF sensor 1”7 is a separator lens plate 18.
are provided, and the separator lens plate 18 has separator lenses 18a corresponding to the photoelectric conversion element arrays 16a to 16c.
-18c are integrally formed.

One aperture mask is provided immediately before the separator lens plate 18, and one aperture mask includes the separator lens 18a.
Openings 19a to 19c corresponding to 18c are formed. A reflection mirror 20 facing the aperture mask 19 and the sub mirror 14 is provided, and the reflection mirror 20 directs the focus detection light beam reflected downward by the sub mirror 14 to the aperture mask aperture 1.
9a to 19c and separator lenses 18a to 18c to lead to photoelectric conversion element arrays 16a to 16c. Between the reflection mirror 20 and the sub-mirror 14, there is a condenser lens 2 facing the aperture mask openings 19a to 19c.
1a to 21c are provided, and condenser lenses 218 to 2
A field mask 2 has openings 22a to 22c on the upper surface of 1c for separating the focus detection light beam so as to correspond to the photoelectric conversion element arrays 16a to 16c having different positions and directions.
2 is provided.

The principle of focus detection is the TTL phase difference detection method, in which different areas 11a and ll of the exit surface of the photographing lens 11 are used.
The reference portion light flux a (indicated by the broken line in FIG. 3) and the reference portion light beam b (indicated by the solid line in FIG. 3) passing through the reference portion A in each of the photoelectric conversion element rows 16a to 16c are
and the reference part B, convert the light distribution pattern of the image into an electrical signal, calculate the correlation between them with a correlator (not shown), perform automatic focus detection, and convert it into a shift signal from the correlator. Automatic focus adjustment is performed by moving the photographic lens 11 back and forth using a drive mechanism based on this.

In the focus detection optical system of FIG. 2, in addition to the horizontally positioned photoelectric conversion element array 16a, the vertically positioned photoelectric conversion element array 16b,
16c, horizontal and vertical focus detection can be performed at the same time, making it possible to detect focus on horizontal lines and the like.

FIG. 4 shows the focus detection area and the display in the finder for the photographing screen of the camera using the AF sensor 17 of this embodiment. In this example, three areas ISI, IS2, and IS shown by solid lines in the center of the screen are shown on the shooting screen S.
3 (hereinafter referred to as the first island, the second island, and the third island, respectively)
It is possible to perform focus detection on objects (referred to as islands).

A rectangular frame AF indicated by a broken line in the figure is displayed to show the photographer the area where focus detection is being performed. A display Lb shown outside the photographing screen S indicates the focus detection state and lights up when the camera is in focus.

Figure 5 shows the light receiving section (of the CCD) used in this focus detection device.
(hereinafter referred to as a CCD including the light receiving section, storage section, and transfer section). Each island S1, IS in Figure 5
2. A standard part and a reference part are provided for IS3, and light receiving elements MPDI and MPD2 for monitoring are provided for each island ISI, IS2, and IS3 to control the integration time to the storage part of the CCD. , MPD3 are provided respectively. The number of pixels (X, Y) in the standard part and reference part of each island IS1, IS2, and IS3 is (34, 44) for island ISI, and (44, 52) for island IS2.
) and (34, 44) in island IS3, all of which are formed on one chip.

In the focus detection device in this embodiment, the reference portion of the CCD of the three islands ISI to IS3 is divided into a plurality of blocks, and the focus detection is performed by comparing the reference portion of the divided blocks with all of the reference portions. conduct. In each island, among the focus detection results obtained in the divided blocks, the data of the rearmost focus is used as the focus detection data of each island, and further, the focus detection data of the camera is calculated based on the focus detection data of each island.

The range to be divided and the defocus range of the divided blocks are shown and explained in FIGS. 6 to 8.

FIG. 6 shows an enlarged view of the focus detection area on the photographing screen S shown in FIG. Each of the focus detection islands ISI, IS2, and IS3 is an area of the reference section shown in FIG. In addition, in FIG. 6, the numerical values shown for each island correspond to 3 of the pixels of the CCD shown in FIG.
Indicates the number of difference data obtained by taking every second difference (difference data may be every second or every second. However, in this case, the above numerical value will be different), therefore, the reference part and the reference part in each island. The number of differential data (x, y) is (30, 40) for island ISI, (40, 48> for island IS2, and (30, 40) for island IS3.
The division on each island is as follows, but island I
In SI, it is divided into two parts, and from the top difference data (1 to 20
>, (11-30), and the first block BL1 and the second block BL2, respectively. In Island IS2, it is divided into three parts, and from the leftmost difference data (1-20), (11-3
0), (21 to 40), and the third block Bj3, respectively.
A fourth block BL4 and a fifth block BL5 are assumed. Further, the phase (1 to 35) of adjacent data of data obtained by taking differences every seventh for all pixels is set as the sixth block BL6, and the front part (1 to 25) of this data string is set as the seventh block BL7,
The rear part (11 to 35) is referred to as the eighth block BL8. For island IS3, from the difference data at the top (1 to 20)
, (11 to 30), and the ninth block BL9 respectively.
, the 10th block BLIO.

In focus detection using this phase difference detection method, when the images of the reference part and the reference part match, when the image interval is larger than a predetermined interval, the rear focus is on, and when it is smaller, the front bin is focused, and the image is focused at the predetermined interval. Therefore, in the defocus range of the divided blocks, the blocks that are far from the optical center of each island have the rear pin side. This will be explained in detail based on FIG. 7, which shows the state after the differential data has been taken.

FIG. 7 shows the reference part and the reference part of the island IS2,
Now, consider the defocus range of the fourth block BL4 divided into blocks. At this time, the images in focus are the 15th to 34th images (15' to 34th) from the left end in the reference section.
4') and the images (11 to 30) of the fourth block BL4 coincide.

From this, when the images match on the left side of the reference part, it becomes the front bin, and at this time, the maximum number of deviation data of the front bin (hereinafter referred to as deviation pitch) is 14, and when the image matches on the right side of the reference part, it becomes the rear bin, and this When the maximum rear pin deviation pitch is 14
becomes. The defocus range divided into blocks in each of the other islands is the same, and this is shown in Figure 8.
In block BL3, the front pin side deviation pitch is 4 and the rear pin side deviation pitch is 24. In the fifth block BL5, the front pin side deviation pitch is 24 and the rear pin side deviation pitch is 4.

For islands ISI and IS3, block BLI
, BL9 has a front pin side deviation pitch of 5 and a rear pin side deviation pitch of 15, and blocks BL2 and BLIO have a front pin side deviation pitch of 15 and a rear pin side deviation pitch of 5. 6th
In block BL6, there are 4 pitches on both the rear pin side and on the front pin side, and in the seventh block BL7, there are 4 to 14 pitches on the rear pin side. Also, in the 8th block BL8, there are 4 pins on the front pin side.
This is 14 pitches.

FIG. 9 shows an AF sensor 17, an AP controller 30, and their peripheral circuits as an example in which the photoelectric conversion device of the present invention is used as a focus detection device of a camera. The AF controller 30 is formed of a one-chip microcomputer, and includes an A/D converter 31 that converts an analog signal obtained from the analog signal output line Vout of the AF sensor 17 into a digital signal, and a photographing lens (interchangeable lens). ), the defocus amount-lens extension amount conversion coefficient is set to be different for each lens, and data such as the color temperature defocus range L is input in advance from the A/D converter 31. A memory section 3 formed of RAM that stores digital data one by one.
2, a focus detection unit 33 that detects a focus based on the output of the memory unit 32, a correction calculation unit 34 that calculates a correction amount from the detected focus data and lens data, etc., and a correction calculation unit 34 that calculates a correction amount based on the correction amount. A lens drive control section 3 that sends a signal for driving the lens to the lens drive circuit 42 and receives data on the movement status of the lens from the encoder 44.
5, and a timer circuit 3 for monitoring whether the integral value (hereinafter also referred to as "charge accumulation") of the AF sensor 17 reaches a predetermined value within a predetermined time.
6, and an AP sensor control section 37 that sends and receives signals to and from the AF sensor 17. Note that 43 is a lens driving motor, and 41 is a display circuit controlled by the AF controller 30. The AF sensor 17 and the AF controller 3o are formed separately with one chip each, so the AF system is comprised of two chips in total. Vref is an analog reference voltage for the A/D converter 31 of the AP controller 30 and the AF sensor 17, Vcc is a power supply line, and GND is an earth line.

Between the AF sensor 17 and the AF controller 30 is an MD
I, MD2. ICG, SHM, CP, ADT.

It is connected by seven signal lines of VouL. Of the seven signal lines mentioned above, MDI and MD2 are signal lines for outputting logic signals from the AF controller 30 to the AF sensor 17, and set the operating mode of the AP sensor 17. There are four operating modes of the AF sensor 17: initialization mode, low brightness integral mode, high brightness integral mode, and data dump mode.
The operation mode is set by a combination of the logic levels of I and MD2. The signal lines ICG and SHM are bidirectional, and in the data dump mode described above,
This is an output logic line from the AF sensor 17 to the AF controller 30, and outputs information regarding the brightness of the subject in each island and the order of completion of integration. In other modes, the signal line ICG receives the ICG signal instructing the AF sensor 17 to start a new resolution, and the signal line SHM receives the SHM signal instructing the AF sensor 17 to request data. It becomes a logic line that supplies to 17. signal line C
P is a line that supplies a basic clock from the AP controller 30 to the AF sensor 17. This signal line CP
The basic clock supplied from the AP controller 30
0N10FF control is possible inside the AF sensor 1, and by turning this basic clock into the OFF state, the AF sensor 1
Temporarily freezes the operation of AF controller 30.
It is also possible for the control unit to control other circuit parts, such as the lens drive circuit 42 and the like. In the data dump mode, the signal line ADT indicates the completion of outputting one pixel data of the AF sensor 17, and the signal line ADT indicates the completion of outputting one pixel data of the AF sensor 17, and
An ADT signal is supplied to the conversion unit 31 to instruct the start of A/D conversion. In other modes, when charge is accumulated to an appropriate level in each island of the AF sensor 17, an interrupt signal is output from the AF sensor 17 to the AF controller 30 to indicate completion of integration.

Finally, the signal line Vout is an analog signal line, and the photoelectric conversion element rows 16a to 16a in the AF sensor 17.
After analog signal processing is performed on the output of the AF sensor 16c, the signal is supplied from the AF sensor 17 to the A/D converter 31 in the AF controller 30. This Vout signal is output for each pixel in synchronization with the above-mentioned ADT signal, and after being A/D converted, is taken into the AF controller 30 as subject image information obtained from the AF sensor 17.

Next, the specific configuration of the AF sensor 17 will be explained using FIG. 10. Photoelectric conversion element rows 16a to 16 are on the left side of 5 in the figure.
c, and the I10 portion with the AF controller 3° is shown on the right. First, the photoelectric conversion element rows 16a to 16c are the fourth
As shown in the viewfinder display in the figure, it is divided into three islands ISI to IS3 arranged in an H shape.
In principle, each is controlled separately. The detailed configuration of the photoelectric conversion element arrays 16a to 16c is shown in FIGS. 11 to 13. Of these, photodiode PD
The portion including main components such as the shift register SR and the like will be explained. As shown in FIG. 11, the photodiode array section 50 includes a plurality of pixel photodiodes PD,
Monitoring photodiodes MPD are arranged in between. One longitudinal end of each pixel photodiode PD is coupled to the source of a first MOS transistor TRI forming a barrier gate.

The drain of this MOS transistor TRI is coupled to the next stage storage section ST, and the gate is coupled to a supply line for BG and other signals (barrier gate signal).

Although the storage section ST is shielded from light by an aluminum film and is not irradiated with light, so-called dark charges are generated. Storage section S
The output terminal of T is connected to the source of the second MOS transistor TR2 forming the integral clear gate CG and the shift gate S.
It is coupled to the source of a third MOS transistor TR3 forming a transistor TR3. The drain of the second MOS) transistor TR2 is coupled to the power supply line Vcc, and the gate is connected to the IC
It is coupled to the supply line of the G signal (integral clear gate signal). On the other hand, the third MOS) transistor TR.

The drain of No. 3 is coupled to the segment constituting the shift register SR, and the gate is connected to the SH signal (shift gate signal).
is connected to the supply line.

The monitor photodiodes MPD are connected to each other at the upper end of the figure, and therefore the monitor output is from these connected monitor photodiodes MPD.
This is the total output of By combining a plurality of monitoring photodiodes MPD in this manner, it is possible to realize a subject brightness monitoring photodiode having a wide field of view.

The physical structure of the photodiode array section 50 is schematically illustrated in FIG. 12, which shows a cross section taken along the line c-c' in FIG.
From the P+ (P-type high concentration impurity diffusion region) applied to the upper N-type region 53 to separate the wall region 52, the N-type region 53 formed by the implantation method, the pixel photodiode PD and the monitor photodiode MPD. The channel stopper 54 is formed of a channel stopper 54, and an N0 film 55 is provided on the surface to suppress the dark output of each photodiode PD to suppress a surface depletion layer. A positive potential is applied to the silicon substrate 51 from the outside, and a ground potential is applied to the intermediate P wall region 52.

Note that the N-type region 53 is formed by phosphorus implantation, and the P-wall region 5
2 is formed by diffusion of boron.

The pixel photodiode PD in FIG. 11 described above,
Monitoring photodiode MPD, first MoS transistor TR1 for barrier gate signal, storage section ST, second MOS transistor TR for integral clear gate (ICG)
2. Third MOS transistor T for shift gate signal
A large number of cascade combinations of R3 and shift register SR are arranged in the horizontal direction, for example, there are 128 if you count the number of segments of shift register SR.

However, as seen at the right end of the array shown in Figure 13,
Pixel photodiode PD, monitor photodiode MPD, barrier gate MOS transistor TR1,
Storage section ST, integral clear gate MOS) transistor TR2, and shift gate MOS) transistor TR3
The number of segments in shift register S is on the right end side.
There are 5 fewer pieces than R. Conversely, shift register S
Only the number of R segments is greater on the right end side. These five segments merely function as photo-charge transfer paths.

In FIG. 13, among the pixel photodiodes PD and the monitor photodiodes MPD, five on the right end and three on the left end are shielded from light by an aluminum film as shown by diagonal lines. These light-shielded photodiodes PD generate dark charges used for dark correction of the output of the pixel photodiodes PD, for example. One part of the photodiode array part is assigned as the reference part A, and the other part is assigned as the reference part B. For example, the reference part A has 44 pixel photodiodes and the reference part B has 52 pixel photodiodes PD and monitor photodiode PD. including combinations of However, structurally, there is no distinction between the standard part A and the reference part B, and they are distinguished by software processing in the AP controller 30, which will be described later.

Regarding the unnecessary portion between Moeki standard part A and reference part B, only the shift register SR is left, and other pixel photodiodes PD and monitor photodiodes MP are installed.
D, MOS transistor TR1 for barrier gate, storage section ST, MOS transistor TR for integral clear gate
2 and shift gate MOS) A part or all of the transistor TR3 is deleted. The pitch of each segment of the shift register SR corresponding to this deleted portion is formed to be larger than the pitch of other portions, thereby reducing the number of transfer locks required to transfer all pixel outputs and reducing the specific charge transfer time. This makes it possible to shorten the .

The monitoring photodiodes MPD are connected to each other so that only those located in the reference portion A (and reference portion B if necessary) are used, and those located in other portions are not used. However, it is desirable to connect the unused monitor photodiode MPD to the power supply line Vcc to stabilize it.
Receiving guidance from other pixel photodiodes PD,
This is because the light may be guided to the photodiodes PD for other pixels, and the photodiodes PD for other pixels will be affected. A portion of the output of the monitor photodiode MPD is given to a capacitor C2 via a MOS transistor Q5, where it is held and connected to a source follower SF2.
automatic gain control output signal AGC through a buffer consisting of
It is output as an OS. MOS) transistor Q2 is for initializing capacitor C2. In order to remove power supply fluctuations and temperature-dependent components of this automatic gain control output signal AGCO3, a drift output signal DO3 from the capacitor C1 is initialized by a MOS transistor Q1 having the same configuration as the MOS transistor Q2 for initializing the capacitor C2.
are generated simultaneously. This capacitor CI includes a transistor Q (MOS) including a diode MD for detecting a drift component, which has approximately the same area as the total area of the monitor photodiode MPD.

connected via. Diode MD is shielded from light by an aluminum film. MOS transistor Q for initialization,
, Q2 are turned on simultaneously during the application period of the ICG signal (fi minute clear gate signal).

Here, the photoelectric conversion element row 16a of this AF sensor 17
Regarding the charge integration mode of ~16c, Figures 14 to 1
This will be explained using Figure 6. FIG. 14 is a potential distribution diagram of a conventional general one-dimensional photoelectric conversion element array. A photoelectric conversion element for one pixel includes a photodiode PD with an overflow gate OG, a barrier gate BG set to a constant potential, and a storage section ST. First, by applying a voltage to the integral clear gate 5TICG, the storage section ST and the photodiode PD for photoelectric conversion are
As shown in figure (a), the previously accumulated charge is discharged to the overflow train OD. This overflow drain OD is designed in common with the power supply line Vcc. By discharging this unnecessary charge, the photodiode P
D, the charge remaining in the top storage part ST is gone, and each pixel has been initialized. Next, this integral clear gate 5
By removing the voltage to TICG, the potential level of the integral clear gate ICG increases, the flow of charge from the storage section ST to the overflow drain OD is stopped, and the photocharge generated according to the intensity of light incident on the photodiode PD is stopped. Thereafter, as shown in FIG. 14(b), the energy flows into the storage section ST via the barrier gate BG and is stored there. This is charge accumulation operation (integral operation)
It is.

Here, if the average value for each pixel of the charges stored in the storage section ST reaches a level appropriate for the subsequent processing circuit and processing operation, or if there is a data request from the AF controller 30, the integral Perform the completion action. As shown in FIG. 14(e), this integration completion operation is performed by applying a voltage to the shift gate SH and lowering the potential level of this gate.
The charge generated at D and accumulated in the storage section ST up to that point is injected into the corresponding shift register SR.

Here, the reason why the storage section ST is provided is largely due to the following reasons. In the AF sensor 17, a highly sensitive photodiode PD with a large pixel area is used so that it can be used even in a low brightness region, and its length NPH generally reaches several hundred μm. On the other hand, the length 15T of the storage section ST is generally about 50 μm due to requirements such as saturation voltage. Now, considering the time required to transfer the charges to the shift register SR in the integration completion operation, it takes about 3 to 5 μSec to transfer the charges from the storage section ST. This is a value that depends on the moving speed of the charge, and is known to increase in direct proportion to the square of the moving distance.

Therefore, if the N product of charges is performed in the photodiode PD without providing this storage section ST, the charge transfer time τ5t-1 is 1pH=200μm, i's
Assuming v=50μm, τSH=5X(ip+/(sT)2=80
u see, and even if a voltage is applied to the shift gate SH to start the integration completion operation immediately after the start of integration, it is necessary to continue this state for 80 μsec.
This is subject to the restriction of the shortest integration time. This results in a reduction in the dynamic range at high brightness.From this perspective, a storage section ST is provided to shorten the charge transfer length at the end of integration and improve the responsiveness of the integration end operation. It is something.

When the above-mentioned integration completion operation is completed and the voltage applied to the shift gate SH is removed, the photodiode PD and the storage unit ST This means that the charges generated in are transferred in parallel to the corresponding shift register SR.

Thereafter, these image information charges are transferred to the shift register SR.
Transfer lock φ1. It is sequentially transferred in the shift register SR in synchronization with φ2, and is read out as an analog voltage from the output signal line O8 in FIG. It turns out. In addition, M
OS) Transistor Q3 is for initializing capacitor C3.

However, the following problem occurs in this integral operation.

■First, there is the problem of dark output. This is because even in a state where no light is incident, electric charges are generated in each part according to its potential level due to thermal excitation or the like. Therefore, the potential level of the photodiode PD is normally set high, and the potential level of the storage section ST needs to be set low due to the charge inflow conditions. The dark output of the PD is several times to several tens of times higher than that of the photodiode PD.
It is common to double the amount. Therefore, most of the dark output, which is a noise component, is actually generated in the storage section ST, which has nothing to do with photoelectric conversion, resulting in a decrease in the S/N ratio compared to a general photodiode PD.

(2) Furthermore, as mentioned above, with the demand for higher sensitivity in photoelectric conversion, shorter integration time control is required. As explained above, the minimum integration time is not only limited by the pulse width of the shift pulse SH, but also by the transfer lock φ3.
Limits are also imposed on the phase relationship of φ2.

Therefore, in this embodiment, in order to reduce the dark output and complete the integration faster, the two integration modes are switched depending on the usage conditions.

First, when inputting image information of a high-brightness object that requires quick integration completion, the signal lines MD 1 and MD 2 described above are input.
By combining the logic of
T-integration mode is selected. Regarding the integral clearing operation and integral operation shown in FIG. 15(a), first refer to FIG. 14(a).
). In the 5Tfi minute mode, only the integration completion operation is different. The photoelectric conversion element arrays 16a to 16c of this embodiment are designed so that the potential of the barrier gate BG disposed between the photodiode PD and the storage section ST can be controlled. During the integral clearing operation and the integrating operation shown in FIG. Set it to
When the average level of the accumulated charge of each pixel reaches an appropriate level for the subsequent processing circuit, or when a data request from the AF controller 30 occurs, the signal causes the barrier gate BG that has been applied to By removing the voltage of barrier gate BG, as shown in FIG.
The potential of is raised to a high level to stop charge transfer between the photodiode PD and the storage section ST, and thereafter
Completion of the integration operation is achieved by prohibiting the charge generated by the incidence of light from flowing into the storage section ST in the photodiode PD. After that, as shown in FIG. 15(b), N'
Raise the potential of f1 ST to a high level,
While the charge from the photodiode PD is held in the storage section ST, the generation of dark charges at the top of M is suppressed to prevent image information from being damaged by the dark charges generated in the storage section ST. .

After this state, in response to the generation of the data request signal SHM from the AP controller 30, as shown in FIG. 15(c), a voltage is applied to the shift gate SH to lower the potential level of this gate. , performs charge transfer between the storage section ST and the shift register SR.

In this way, the data readout and the integration completion operation are performed separately, and the integration completion operation is realized simply by changing the potential of the barrier gate BG from a low level to a high level, thereby achieving extremely high responsiveness of the integration completion operation. It has been realized.

Pressure I Light i: 5 (Low Calculation Precision Mode) Next, the integration mode of the photodiode PD for a low-brightness subject requiring reduction of the dark output will be described using FIG. 16. The integration mode of this photodiode PD is such that the photodiode PD has a low dark output and the charge is accumulated 1 (f
i minutes) and discharge unnecessary dark output generated in the storage section ST during this integration via the integration clear gate 5TICG. In this mode, after the generated charges are transferred to the shift register SR, they are sequentially read out. In this mode, since it is subject to the above-mentioned charge transfer speed limitation, a time of about 100 μseQ is required to complete the integration operation, but image information can be read out with extremely low dark output.

The integral clearing operation is performed in exactly the same manner as shown in FIG. 14(a). Next, at the beginning of the integration, Figure 16 (
As shown in a), unlike the integration mode shown in FIG. 14 and the ST integration mode shown in FIG. The charge is stored in the photodiode PD instead of the storage unit ST. The charge accumulated in this photodiode PD reaches an appropriate level, or the data request signal S from the AF controller 30
When performing the integral completion operation by HM, first the storage section S
The unnecessary dark output charges generated at T and accumulated in the accumulation section ST are discharged.
As shown in b), unnecessary charges remaining in the storage section ST are discharged by manipulating the potential of the integral clear gate 5TrCG. After discharging the unnecessary charges from the storage section ST in this way, as shown in FIG. Charge transfer between PD and storage section ST is performed (see FIG. 16(c)). As described above, this charge transfer requires a time of about 100 μsec, and is clocked and operated within the AF sensor 17. After completing the transfer of the charge integrated by the photodiode PD in this way, the potential of the barrier gate BG is returned to a high level again, thereby completing the integration completion operation.

Also, after the completion of this integral operation, as shown in FIG. 16 (cl)
As shown in FIG. 3, the potential of the storage section ST is set to a high level to suppress the generation of dark charges, which is the same as after the end of the ST integration mode described above.

After waiting in this state, the shift gate SH is operated by the data request signal ST (M) from the AF controller 30, and charges are transferred in parallel from the storage section ST to shift I to register SR. The read operation is also as described above.

The photoelectric conversion element array t shown in the block diagram of FIG.
Having finished the explanation of each of the photoelectric conversion element arrays 16a to 16c, a description will now be given of how these photoelectric conversion element arrays 16a to 16c are controlled in this embodiment. As shown in FIG. 10, each of the three photoelectric conversion element rows 16a to
Monitor photodiode MPDI~M in 16c
CCD integration time control units 171-173 are provided for each output AGCO31-AGCO33 of PD3, respectively, and barrier gates BG1-BG1 of each island ISI-IS3 are provided.
BG3, storage section ST1 to ST3, integral clear gate ST
I CG 1-5TrCG3 are controlled.

Further, one CCD clock generation section 174 exists for all islands, and a common transfer lock φ1. It controls φ2 and the shift gates SH1 to SH3 of each island.

Below, regarding the ST integration mode for high-n degree subjects,
This will be explained using the time chart of FIG. 17(a). First, the AF controller 30 sets the signal line MD1 to the "Loud" level and the signal line MD2 to the "High" level in order to set the high brightness integration mode.Next, in order to set the AP sensor 17 to start integration, , I.C.G.
Provides a signal (integral clear gate signal). This IC
The G signal is supplied to each CCD integration time control section 171-173 via the I10 control section 175 in FIG. A 5TICG signal (ST integral clear gate signal) is supplied from each CCD integration time control section 171 to 173 to each photoelectric conversion element array 16a to 16c for a time (approximately 100 μ5ec) sufficient for the above-described charge discharge. During this time, the barrier gates BGI of the photoelectric conversion element rows 16a to 16c of each island
A high level voltage is also supplied to BG3, and the charges generated in the photodiode PD are all discharged to the overflow drain OD via the pass gate BG, the storage section ST, and the integral clear gate STICG.
After approximately 100μ5ec), only the 5TrCG signal becomes 'Low' level, and the ST[minute clear gate 5TI
The potential of CG becomes high level, and the charge generated in photodiode PD starts to be accumulated in storage section ST. On the other hand, this 5TICG signal causes each output AGCO3 of the monitor photodiodes MPD1 to MPD3 to
Integration is also started for I~AGCO93. The details will be explained below.

Figure 18 shows monitor photodiodes MPD1 to MP
AG for integrating each output AGCO31 to AGCOS3 of D3 and obtaining voltage flag signals VFLcl to VFLC3.
The details of the C signal processing circuit 60 are shown, and FIG. 19 is a time chart thereof. This AGC signal processing circuit 60
are provided in each CCD integration time control section 171-173. When the ICG signal is input, "
A 'High' level signal is supplied to initialize the voltages ΔV DO5 and ΔV ACC of the capacitors CI and C2.At the same time, the operating point of the inverting amplifier 64 is set using the operating point setting pulse φF, and the initializing pulse The capacitor C6 of the reference output holding unit 65 is initialized by φS, and the capacitor JLC7 of the comparison circuit unit 66 is initialized by the initialization pulse φFLGR9.The voltage Δv oos of the capacitors C1 and C2
and Δv Acc are differentially amplified in a differential amplification section 61 which is a combination of source followers, and the automatic gain control voltage VAcc after subtracting the drift output signal is 0.8.
X (ΔV ACC−ΔV oos) +■o is obtained. Here, Vo is an offset value. Differential amplifier section 6
The automatic gain control voltage V M;C obtained from 1 and the reference voltage Vr obtained from the reference voltage generation section 62 are synthesized in a voltage synthesis circuit section 63 including capacitors C4 and C5 of the same capacity. The output voltage Vx of this voltage synthesis circuit section 63 is 0.8X ((ΔV AGO−ΔV oos)
A variation component of V rt/2 is obtained. If the automatic gain control output signal is AGCO3, ΔVAGC=ΔV 0
0s+V+AGCO8. Here, Vl is the offset value. From this, VACC=0.8X(-A
GCO3)+V2. Kokote, V2 (=Vo+0.
8XV, ) is also an offset value. Further, the output voltage Vx of the voltage synthesis circuit section 63 has a fluctuation component of (0,8
h" level, φb to φe are "Lo4" level, so the reference voltage V" has the minimum reference voltage Va (= 0.37
5 V) is supplied. The voltage Vy-(10)xVx obtained by inverting and amplifying the output voltage Vx of the voltage synthesis circuit section 62 at this time in the inverting amplifier section 64 is the voltage flag signal V FLC.
; This becomes the inversion threshold level, and this voltage Vy
is held in the capacitor C6 of the reference output holding unit 65 at the falling timing of the initialization pulse φS, and continues to be supplied as level VYA. Next, the initialization pulse φF falls, and the total charge at this time is held in the capacitors C4 and Cs of the voltage synthesis circuit section 63. After that, the level fluctuation of half of each voltage fluctuation in each of the input voltages VAco and Vr of the voltage generator circuit section 63 becomes the level fluctuation of the output voltage Vx. Next, the AF controller 30 controls the reference voltage Va
(=0.375) and the initialization pulse DO3R3 are set to the "Low" level, and then the pulse φe to obtain the reference voltage Ve (=3.375 V) is set to the "High" level. The fluctuation of voltage VACC is (Ve
-Va), initialization pulse φFLCR9 is set to Low''' level, initialization pulse AGCR8 is set to "Loud" level 1, and integration of the monitor output is started.For monitoring The light incident on the photodiode MPD is photoelectrically converted, and the generated electrons change the voltage Δv Aco charged in the capacitor C2 to the initial value Vcc.
Gradually decrease from Then, the variation from the initial value in the output voltage Vx of the voltage synthesis circuit section 63 is (-Va + 0.8 It becomes the same potential as VYM, and further V y)
When V sB # 0, 8
is inverted and output as a signal indicating the appropriate level of integration.

The AGC signal processing circuit 60 is configured by such a circuit, but in the AP sensor 17 of this embodiment, the area of the pixel photodiode PD in each island is made common, and the sensitivity of each COD pixel is made common. At the same time, a monitor photodiode M in each island
By standardizing the total area of the PDs, the sensitivity ratio of the pixel photodiodes PD and the monitor photodiodes MPD in each island can be made the same, and as a result,
The reference voltage generating section 62 in the AGC signal processing circuit 60 shown in FIG. 18 is shared by each island, making it possible to save power consumption in the voltage dividing resistor group R and to reduce the chip area of the AF sensor 17.

Furthermore, this AGC signal processing circuit 60 not only controls the integration time of the CCD pixel array in each island, but also controls the integration time of the CCD pixel array in each island.
Even when the maximum allowable integration time of the system is measured in a state where integration is insufficient, appropriate gains are provided depending on the monitor signals from each island. Determination of this gain is also the role of this AGC signal processing circuit 60.

SH to start reading data from the AF controller 30
When the M signal is supplied, the COD integration time control section 171~
173 starts a forced completion operation of the refinement operation, and starts operating the barrier gates BGI to BG3, storage sections STI to ST3, and ST integral clear gates 5TICGI to 5TICG3. In ST integration mode, barrier gate B
GI~B G, Instantly with only 3 operations, PDi
In 'ii minute mode, after applying the SHM signal, S
T performance performance real game) ST I CG 1~5 TICG
3. Approximately 100 by operating barrier gates BGI to BG3
After μsec has elapsed, the integration completion operation is completed. Subsequently, a shift pulse S is first applied to transfer charges from the storage section ST of the second island to the shift register SR.
H2 is generated. At this point, it is necessary to memorize the gain of each island.

Therefore, following the generation of this shift pulse SH2, the monitoring reference voltage Vr of each island is sequentially switched using the reference voltage switching pulses φe, φd, φC1φb, and the inversion of the voltage flag signal VFLC is checked, and it is determined at which point. The gain at the time of reading out the photoelectric conversion signal of each island is determined depending on whether or not the voltage flag signal vFLc is inverted, and is stored in memory.

Voltage flag signal VFLG when Vr=Ve (3,375V)
The reversal of Vr=Vcl(1,87
5V), if the voltage flag signal VFLC is inverted, the gain of ×1 is memorized and the V
If the voltage flag signal VFLC is inverted at the time of switching from r - V d to Vr = Vc (1,125 V), the gain of ×2 is memorized, and V r = V
At the time of switching from c to Vr=Vb (0,75V), the voltage flag signal V FL (if an inversion of 2 occurs, ×
A gain of 4 is memorized, and if the voltage flag signal VFLC is not inverted even when switching to V r = V b, a gain of ×8 is memorized. In this way, the gains are simultaneously determined and memorized by the AGC signal processing circuits 60 of each of the first, second, and third islands, and then when the pixel data of each island is read, the memorized gains are determined as shown in FIG. The most appropriate gain is supplied to the output of each island. Further, the gain information of each island is outputted as digital data in synchronization with the ADT signal immediately after the start of data dumping from the ICG and SHM signal lines to the AF controller 30.

The AGC signal processing circuit 60 as described above is connected to each CCDIC.
are provided in the D-interval control units 171 to 173, respectively,
Each of the monitor outputs AGCO5I to AGCO33 is constantly monitored by the AGC signal processing circuit 60 to determine whether or not it has reached an appropriate level.
3 is detected, each time the voltage flag signals VFLc1 to VFL of that island ■S1 to ■S3 are detected.
Cz is inverted. In the operation example shown in FIG. 17, first, the voltage flag signal VFLC2 is inverted in the second island. At this point, the CCD 1-minute time control unit 172 inverts the barrier gate signal BG2, which had been outputting a 'High' level signal from the integral clearing operation, to a 'Low' level, thereby reducing the charge between the photodiode PD and the storage unit ST. The inflow is cut off, the integration is completed, and the ADT signal, which had been kept at the "High" level since the time the integration was cleared, is changed to °'Low.
By supplying a level pulse signal, the AF controller 30 is notified of the completion of integration for one island.A
The F controller 30 can recognize the completion of integration for one island by inputting the fall of this ADT signal as an interrupt signal and performing ADT interrupt processing (described later in FIG. 25). .

In the case of the islands in the pond, that is, in the case of FIG. 17(a), the barrier gate signals BGI and BG3 remain at the ``High'' level for the first and third islands, regardless of the operation of the second island. , perform the continuation of the integral (
This operation is limited to the STM minute mode, and in the PDfit minute mode, which will be described later, the integration of all islands is stopped at the same time. ), in the operation example of FIG. 17(a), the second
Next to the island is the voltage flag signal VF of the first island.
An inversion of LC+ has occurred. In this case, as in the case of the second island, the ADT signal is
Outputs 11 level pulses and outputs barrier gate signal BGI
is inverted, the connection between the photodiode PD and the MTrt section ST is cut off, and the integration completion operation is performed. AF controller 30
recognizes the completion of the integration of the second island at the fall of this ADT signal. Finally, if the voltage flag signal V FLC3 of the third island is inverted before the maximum allowable minute time (20 m5ec in ST integration mode) has elapsed, the ADT signal is held at I Lo, , I + level and the barrier The gate signal BG3 is set to the LOLI+'' level, the connection between the photodiode PD and the storage section ST is cut off, and the integration is completed. By repeatedly sensing the ADT signal, it is possible to detect that a signal at the low I+ level is continuously output, and to recognize that the integration of all islands has been completed.

At this point, the photoelectric conversion element arrays 16a to 16 of all islands
In the accumulation section c, an amount of charge at a level suitable for the subsequent analog signal processing section 176 is prepared and held.

Next, the AF controller 30 sends the S
The HM signal is supplied to the AF sensor 17.

This SHM signal is transmitted to each CCD integration time control section 171 to 173 and the CCD through the I10 control section 175 in FIG.
The signal is supplied to the clock generating section 174.

As shown in the time chart of FIG. 17, before the SHM signal is supplied to all islands, the CCD integration time control unit 171
-173, when the integration operation is automatically completed, the CCD integration time control units 171-173 control this SHM.
Does not work on signals. On the other hand, the CCD clock generator 174 initializes the internal counter with this SHM signal, starts counting the input pulse CP from this point, sets the transfer lock φ1 to the "High" level, and sets the transfer lock φ2 to the "L" level. ow'' level and first supplies a shift gate pulse SH2. By applying this shift gate pulse SH2, the charge held in each storage section ST2 of the second island is transferred to the shift register SR2 of the second island. Shift gate pulse S H2
After the application of φ1. φ2 is restarted and this transfer lock φ1. In synchronization with φ2, the shift register SR2 of the CCD sequentially transfers the photocharges generated in the photoelectric conversion section of the second island as an output signal OS2. C.O.
The D clock generator 174 counts the number of CCD transfer locks and sends it to the analog signal processor 176.

Furthermore, when outputting an analog signal from the CCD dark output pixels, which are the 7th to 9th pixels shown in FIG. 13, the analog signal processing unit 176 Supplies control signals for level clamping.

Details of this analog signal processing section 176 are shown in FIG. 20, and its operation timing is shown in FIG. 21. The analog signal processing unit 176 includes buffers 71 to 73 that receive output signals O81 to O33 of the respective photoelectric conversion element arrays 16a to 16c, and one of the outputs of the buffers 71 to 73 is output according to the output timing. Analog switch ASI~A
It is selected in S3 and input to the AGC amplifier 74.

The output of the AGC amplifier 74 is sampled and held in a sample and hold circuit 75, and the reference level is clamped to the reference voltage Vref in a level clamp circuit 76, resulting in an output signal (2). Output as S. The level clamp circuit 76 receives level clamp control signals CE1, CF2, AR33, AR34, and CLl from the CCD clock generator 174.
, CF2.

Further, the CCD clock generator 174 outputs the ADT signal to I1.
0 control unit 175. This ADT signal is C
The ADT signal is output as a signal indicating switching between one pixel and one pixel of the CD data, and the A/D conversion section 31 starts A/D conversion at the falling edge of this ADT signal. These CCD transfer locks φ1. A time chart showing the operation of φ2 and each signal synchronized therewith is shown in FIG. Furthermore, this ADT
As shown in FIG. 17(a), the signal is output at the time of the falling pulse indicating the completion of the integration of each island, and at the time of the output of the ■C
It is output as a signal synchronized with the CCD transfer lock only when outputting digital data using the G and SHM signal lines and when outputting a valid pixel, and is masked by the counter value in the CCD clock generator 174 when outputting an invalid pixel. , no output.

Therefore, on the AF controller 30 side, it is possible to import A/D conversion data without determining whether a pixel is a valid pixel or an invalid pixel.

In this way, the image signal photoelectrically converted in the second island is outputted as an output signal Vos to the reference section and then to the reference section. This image signal is an output obtained by clamping the dark output level generated during the integration time of the second island to the reference voltage Vref. Next, it is necessary to read out the image signal photoelectrically converted in the first island. Therefore, as shown in FIG. 22, the clock φ1 at the time of outputting the 48th pixel data of the reference unit output in the second island is “High”.
The SHI signal is generated at the phase of the "level." This timing is also derived from the value of the counter in the CCD clock generator 174. At this point, the SHI signal is generated at the beginning of the CCD output as shown in FIG. This is because there are skip-feeding pixels that do not have any pixels, and the purpose is to shorten the output time of these skip-feeding pixels.After this SHI signal is generated, the 52nd pixel data of the reference section in the second island is output. Once completed, the CCD clock generator 174
The AS2 signal for opening/closing control of the analog switch AS2 in the analog signal processing unit 176 is changed from the “High” level to the “Lo” level, and the AS1 signal is changed to the “LOL11” level.
The level is switched from the low level to the "High" level, and the data of the first island is supplied to the analog signal processing unit 176. After this, as in the case of data output from the second island, after sampling and holding the dark output, the analog signal V
The dark output level generated during the integration time of the first island is clamped to the A/D conversion reference voltage Vref from out, and is output to the reference section and then the reference section in that order from the second island to the first island. By performing exactly the same process as when switching the output to the island, the output is switched from the first island to the third island, and data is output from the third island. This completes the data output and moves on to the next integration.

In the analog signal processing section 176 shown in FIG. 20, the output signal Vos becomes unstable during the integration time and during the clamping operation of the dark output level, so it is not suitable as a signal to be supplied to the outside.

Therefore, during these phases, the A/D conversion reference voltage V
The CCD clock generator 174 controls the temperature data V TEMP obtained by dividing ref by resistors having different temperature coefficients to be the output signal Vout. Temperature data V T
EMP is supplied from a temperature detection section 177 shown in FIG. 10 to an analog signal processing section 176.

Next, in the PDi minute mode for low-brightness subjects, since the low brightness has a long integration time, priority is given to the speed of the entire system, and as shown in Figure 17 (b), the maximum integration time (
100m5ec) or when the first ADT signal is input from the AF sensor 17 to the AP controller 30, the AF controller 30 sends the AF sensor 17
The SHM signal is supplied to all islands ■S1 to ■S3.
The refinement operations in are completed at the same time. Except for this point, the operation is roughly the same as in the 5Tff minute mode described above, so a redundant explanation will be omitted, and this concludes the explanation of each operation in the ST integration mode and the PD integration mode.

By the way, the voltage flag signals VFLC+ to VFLC:1 of each island in the AGC signal processing circuit 60 described above are outputted as the falling edge of the ADT signal, and cause the AF controller 30 to recognize the timing of completion of integration. However, the AF controller 30 can only recognize from the ADT signal that the integration has been completed on one of the islands, and the island on which the integration has been completed can only be determined from the ADT signal. Therefore, the AF controller 30 is made to recognize the order in which the integration of each island is completed using digital data from a later data dump. This allows the AP controller 30 to know the timing of completion of integration in each island and the order of completion of integration, and based on this information, corrects the amount of lens movement during the integration time and during focus detection calculation. It can be performed. In other words, when moving the lens for automatic focus adjustment, A
There is a time difference between the time of integration by the F sensor 17 and the time when the further lens drive amount is calculated as a result of focus detection calculation based on the effective pixel output of the AF sensor 17.
It is necessary to correct the l/lens movement amount during this time. In the ST integration mode in which the point of completion of integration differs for each island, the amount of correction of the lens movement amount differs for each island.

The focus detection operation during lens drive will be described below using the time chart of FIG. 23. Now, when the lens is being driven at a constant speed, the image is projected onto the AP sensor 17 (an image that changes at any time according to the driving of the lens is projected, and the image interval that has changed is calculated. However, as long as there is no change in subject brightness, the image interval will match the image interval obtained at the midpoint of the integration interval of the AF sensor 17. Integration is now started from time t.
Assuming that the integration of the first island is completed at time l, the third island is completed at time t2, and the second island is completed at time t3, the result of the focus detection operation calculated at time , is the image at different times for each island. It is calculated as defocus fitclf, ~df, based on the interval. In other words,
On the first island, time 11=(t.

+t, )/2, and on the second island, time l2=(to+
t:+)/2, and on the third island, time I 3 = (
The defocus amount drl~clf is calculated for each island based on the image interval at the time of to + t2)/2. When converted into the number of drive pulses based on these values df1 to df, N1 to N3 are calculated, respectively. However, the number of drive pulses N1 to N3 calculated here is the number of drive pulses required at the integration center for each island (times 1 to 13 at the middle point of the integration interval), respectively.
It is first necessary to convert this into the remaining number of drive pulses R1 to R3 at the time when the focus detection calculation is completed. Therefore, time t
, , t+ +t2+t3, the pulse count value indicating the lens driving amount is stored in the counter register CT(1
) ~ CT (4) It is necessary to store it in memory. The pulse count value indicating the amount of lens drive at each point is P (to
), p (t+>, P (t2), P (t3), the pulse count value indicating the current lens drive amount is p (t<
), the remaining number of drive pulses R1 to R3 at each island IS1 to IS3 is calculated by focus detection calculation using the pulse count value driven from each integration center 11 to I3 until the focus detection calculation completion time t4. The values are obtained by subtracting the number of driving pulses N1 to N3, which are expressed by the following equations.

R1= N 1 + P (t4>-(P (t,)+
P (t+))/2R2= N 2 + P (t
, )−(p (t,) + p (ts))/2R,
3= N 3 + P (t,)-fP (t,)+
P (t2))/2 In this way, the defocus amount of each island S1 to IS3 (at this point, it is converted to the pulse count number R1 to R3) viewed from the same point is calculated, and the defocus amount of each island S1 to IS3 is calculated for the first time. At this point, it is determined which island's defocus amount is to be used for lens driving.

As explained earlier, the time chart in FIG. 23 shows changes in the ICG signal and SHM signal transmitted between the AP sensor 17 and the AP controller 30, and the voltage flag signals VFLC+ to VFLCI in the AF sensor 17. It shows.

Here, the integration completion signal of each island is recognized by the AP controller 30 as the falling edge of the ADT signal, and is also recognized by the AP controller 30 as the falling edge of the ADT signal.
The AF controller 30 detects the change to "Low" level, and then detects that the ADT signal is maintained at the 11 Lo III level, and recognizes that the integration of all islands is complete.At this point, the voltage flag signal v
All of FLC+ to VFLC3 are inverted, and I10 control unit 1
Six D flip-flops FF12.
FF13. FF21. FF23. FF31. The order of completion of integration is stored in the FF 32. In the operation example shown in FIG. 23, the voltage flag signal VFLCI becomes °'Hi at time t.
At this time, the clock power of the D flip-flops FF21 and FF31 rises from the "Low" level to the "High" level, and the voltage applied to the data voltage The "High" level signals of the flag signals VFLC2 and VFLC2 are latched to each output Q. As a result,
The D flip-flops FF21 and FF31 memorize that the integration completion time of the first island is earlier than the integration completion time of the second and third islands.Next, at time t2, the voltage flag signal "FLC:l" becomes "High". At this time, the clock signal CK of the D flip-flops FF13 and FF23 rises from the "Low" level to the "High" level, and the voltage flag signal VFLQ+ applied to the data signal is reversed. 'L
ow" level signal and the voltage flag signal VFLC2 "
A "High" level signal is latched to each output Q. As a result, the D flip-flops FF13 and FF23 complete the integration of the third island later than the first island, and the second island completes the integration later than the first island. Furthermore, at time t, the voltage flag signal ■FLC2 changes from the “High” level to the L level.
At this time, the clock input CK of the D flip-flops FF12 and FF32 becomes "Low".
The voltage flag signal V FLC rises from level to °'Higb°' level and is applied to that data input.
The "Lo4'" level signal of I, V FLG3 is latched to the output Q. As a result, the D flip-flops FF12 and FF32 determine that the time when the integration of the second island is completed is different from the time when the integration of the first and third islands is completed. Remember that it is also slow.

The outputs Q of these six D flip-flops are sent to A via signal lines ICG and SHM as digital data immediately after the data dump starts, along with the gain information of each island.
The signal is transmitted from the P sensor 17 to the AF controller 30.

A flowchart for performing the lens movement amount correction described above is shown in FIG. 25 and will be described. First, when the first focus detection is started, there is no lens drive and the memory values of each counter register CT(I) are the same, so lens movement amount correction is not performed and defocus, idf, ~df ,
Accordingly, the number of drive pulses N1 to N3 is calculated and set as is in a pulse counter for lens drive, and lens drive is started.

After that, the second integration of the AF sensor 17 is started. FIG. 25 shows the processing after the start of AP during lens driving from the second time onward. The pulse counter for driving the lens has its pulse count value decremented by one each time a pulse corresponding to the amount of lens driving is obtained from the encoder 44.

At the integration start time L0 of the AF sensor 17, the AP controller 30 first stores this pulse count value p (to) in the first counter register CT (1), and then interrupts with the ADTD signal to recognize the completion of integration. 20m5ec when in 5Tfi minute mode, 100...Sec when waiting in PD integration mode, and continues to check whether the maximum integration time has elapsed (#1, #2), when in STT minute mode where the subject is bright , each island automatically completes the integration one after another and becomes in a state where the charge is held in the storage section ST, and each time the ADTD signal goes to "Low" level and an interrupt routine is called by the ADTD signal.

In this routine including ADTD, first, it is determined whether it is the STT minute mode or the PDD minute mode (#15). monitor output AG
According to CO91~AGCO33, charges are accumulated with different integration times, and ADTD is divided into three islands ISI~IS
3 falls at the timing when the integration is completed, and A
The interrupt routine for the DTD signal is called, but since the PD tracking mode follows the fall point of the ADTD signal from the brightest island ISn and charges are accumulated in the same integration time, the interrupt routine for the ADTD signal is called once. This is because it is only called.

Regarding switching of this integral mode, in Fig. 25,
In the diagrams #20 to #25, TINT means integration time. First, when AF is started, the photoelectric conversion element array is initialized, and then the maximum integration time is 20I.
Set to Ilsec PDD minute mode. Then, if the integration is completed within llllsec, PD
Since there is a large amount of excess integration due to the integration completion operation after the integration voltage flag signal VFLc is inverted, the integration mode is changed to the ST top mode and reintegration is performed (#20, #21). Next, if the integration time is less than 10 wheels, the subsequent integration mode is set to STT minute mode and the process proceeds to focus detection calculation (#2
2. #23), If all the gain information of all islands is twice or more, the integration mode remains PDi1D mode, the maximum integration time is changed to 100 m5ec, and the process proceeds to focus detection calculation (#24.#25). Finally, if none of these conditions are satisfied, the integration mode remains unchanged and focus detection calculation is performed.

These integration modes are switched every time the integration of the photoelectric conversion element array is completed, and when the -degree ST integration mode is selected, that is, when the integration time is less than 10 m5ec, the integration time of all islands is changed. The STT minute mode continues until the gain becomes 20 m5ec and the gain doubles or more, and when the mode becomes - degree PD integration mode, that is, when all the islands have an integration time of 20 m5ec and the gain doubles or more. The integration time of one island is 10...
The PDD minute mode continues until the See is turned off.

In this way, by providing hysteresis in the switching condition so that when the integration mode is entered into the integration mode by -degree, the switching condition is provided with hysteresis so that the integration mode is continued, stable data can be obtained in the same integration mode.

First, in the case of ST integration mode, at the first ADT interrupt, at the second ADT interrupt, when the interrupt occurs, t+,
Store the remaining drive pulse numbers p (t+) and p (tz) of h in the second counter register CT (2) and third counter register CT (3), respectively #16), and set the counter register number ■ to 1. After incrementing #2
Return to checking the elapsed maximum integration time (#17, #18
), when the third ADT interrupt occurs and the integration of all islands is completed, the fourth counter register CT (4)
After storing the remaining drive pulse number p (ti>) in , data dump should be started (SHM signal supply (#
Proceed to 3).

On the other hand, in the PD integration mode, the integration of all islands is completed when the first ADT interrupt occurs, so when an ADT signal interrupt occurs, the second, third, and fourth counter registers CT(2) ~ After memorizing the pulse count value p (t) at the ADT interrupt generation time t in CT (4) (#19), supplying the SHM signal for data dump (
Proceed to #3).

On the other hand, if the integration of all islands is not completed even after the maximum integration time has elapsed in #2, the SHM signal for data dump is supplied in #3, and the ADT signal is set to LoIl in #4.
”Confirm that the
~ The pulse count value at that point is memorized in a register that has not been memorized yet among the fourth counter registers CT (2) ~ CT (4'), and the data dump (
Proceed to #8).

Next, the AP sensor 17 outputs AGC data and digital data indicating the order of completion of integration for each island from the signal lines ICG and SHM in synchronization with the ADT signal.
The F controller 30 inputs the digital data.

After that, from the AF sensor 17 to each photoelectric conversion element 16a~
The analog signal output of 16c is connected to the analog signal line Vo.
Since the output is from ut, the AP controller 30
In synchronization with the T signal, this analog signal output is A/D converted and inputted sequentially (#8). All outputs from the AF sensor 17 are A/D converted, and when the data input is completed, this photoelectric conversion element According to the outputs of columns 16a to 16c, focus detection calculations are performed for each island to calculate the defocus amounts dfl to df3 for each island (#9), and then the calculated defocus amounts dfl to df3 for each island are calculated (#9). In order to correct the movement during lens driving for df3, the order in which the integration is completed for each island is determined based on the digital data from the AF sensor 17 (#10), and then the Defocus amount dfl~df3
is converted into the number of driving pulses N1 to N3 using the lens data (conversion coefficient KL) (#11). Next, the number of driving pulses from the integration center of each island ■1 to ■3 until the completion of this focus detection calculation is calculated. calculate. This is the second to fourth counters CT (2) to CT (4
), select one CT(I), and calculate the lens movement correction amount ΔN(I)=CT(5)icT(1)×CT(1
))/2 are calculated respectively. The sign of this ΔN(I) is negative. In the operation example shown in FIG. 23, the lens movement correction amount ΔN(I) for the number of drive pulses N1, N2, and N3 for the first, second, and third islands is ΔN(2), ΔN(4),
This lens movement correction amount ΔN(I), which is ΔN(3), is added to the number of drive pulses N1 to N3 for each island to calculate the remaining drive pulses R1 to R3 for each island (#1
2). Then, from these remaining drive pulse numbers R1 to R3, the drive pulse number RO for the next lens drive is selected (#13). The lens is driven (#14) in accordance with this drive pulse number RO, and the next COD integration (#1) is started.

[Effects of the Invention] As described above, the present invention includes a plurality of photoelectric conversion element arrays that can operate in different charge accumulation modes, and a charge accumulation control section that controls the charge accumulation operation of each photoelectric conversion element array, Since the charge accumulation mode of each photoelectric conversion element array is switched under the control of the charge accumulation control section, the charge accumulation operation of the plurality of photoelectric conversion element arrays can be appropriately controlled, and the charge accumulation operation can always be performed properly. This has the effect that an output with a good S/N ratio can be obtained at the level.

In particular, at high brightness, by controlling the charge accumulation time of each photoelectric conversion element array separately according to the amount of incident light, it is possible to obtain a sufficiently large output without saturating the output. By using a charge storage element array having a smaller area than the light-receiving element array and holding the accumulated charges in the charge N product element array, there is an effect that the readout time of the accumulated charges can be shortened.

On the other hand, at low brightness, by making the charge accumulation time of all photoelectric conversion element arrays the same, it is possible to prevent deterioration of the S/N ratio due to charges in the dark.
By accumulating charges in the light receiving element array and retaining the accumulated charges in the charge accumulating element array, there is an effect that the influence of dark charges can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of the present invention, FIG. 2 is a perspective view of a focus detection optical system in a camera using a photoelectric conversion device according to an embodiment of the present invention, and FIG. 3 is a perspective view of the focus detection optical system of the same. A diagram explaining the principle, Fig. 4 is a diagram showing the display in the finder of the same camera, and Fig. 5 is a diagram showing the C used in the photoelectric conversion device shown above.
An explanatory diagram showing the details of the CD chip, Figure 6 is the same CCD as above.
FIG. 7 is an explanatory diagram showing the details of the central part of the CCD chip, and FIG. 8 is an explanatory diagram showing the amount of shift for each divided region in the CCD chip. , FIG. 9 is a block circuit diagram of an AP sensor and AF controller that realize the photoelectric conversion device as described above, FIG. 10 is a block circuit diagram of the AP sensor as described above, and FIG. 11 is a main part of a photoelectric conversion element array used in the same as above. FIG. 12 is a cross-sectional view taken along line c-c' of the same as above, FIG. 13 is a diagram showing the overall structure of the photoelectric conversion element row of the same as above, and FIGS. 14 to 16 are photoelectric conversion of same as above. An explanatory diagram showing the different integration modes of the device, FIG. 17(a) is an operation waveform diagram of the ST integration mode and data dump mode of the photoelectric conversion device same as the above, and FIG. 17(b) is the PDff component of the photoelectric conversion device same as the above. Figure 18 is a circuit diagram of the AGC signal processing circuit used in the above AF sensor, Figure 19 is an operation waveform diagram of the same mode and data dump mode, Figure 20
The figure is a circuit diagram of the analog signal processing unit used in the above AF sensor, Figures 21 and 22 are operation waveform diagrams of the above, and Figure 23 is a circuit diagram for explaining signal transmission between the above AF sensor and the AP controller. Operation waveform diagram, Figure 24 is a circuit diagram of the integration completion order storage circuit used in the above AF sensor,
FIG. 25 is a flowchart showing the operation of the main parts of the AF controller same as above. 1a to 1c are photoelectric conversion element arrays, 28 to 2c are charge accumulation control units, PDa-S-PDc is a light receiving element array, STa-ST
c is a charge N-element array. Figure 1

Claims (4)

[Claims] (1) Equipped with a plurality of photoelectric conversion element rows that can operate in different charge accumulation modes and a charge accumulation control section that controls the charge accumulation operation of each photoelectric conversion element row, and each photoelectric conversion element row has a charge accumulation control section. A charge accumulation type photoelectric conversion device characterized in that a charge accumulation mode is switched and controlled under the control of. (2) The different charge accumulation modes are characterized by a mode in which each photoelectric conversion element row is controlled with the same charge accumulation time, and a mode in which each photoelectric conversion element row is controlled with a separate charge accumulation time. The charge accumulation type photoelectric conversion device according to claim 1. (3) The photoelectric conversion element array includes a light-receiving element array and a charge storage element array, and the different charge accumulation modes are a mode in which charge is accumulated in the light-receiving element array and a stored charge is retained in the charge storage element array; 2. The charge accumulation type photoelectric conversion device according to claim 1, wherein the charge storage type photoelectric conversion device is in a mode in which charge is accumulated in the element array and the accumulated charge is held in the charge storage element array. (4) The charge accumulation type photoelectric converter according to any one of claims 1 to 3, wherein the charge accumulation mode is switched based on the amount of light incident on the photoelectric conversion element array or the length of charge accumulation time. conversion device.