JPH02170569A - Mos type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To protect an integrated circuit of this design against etching at the patterning of the gate electrode wiring of a semiconductor substrate by a method wherein a conductive material buried in an opening is brought into contact with a wiring under an interlaminar insulating film. CONSTITUTION:An interlaminar insulating film 10 on a source/drain region 8b, a gate electrode wiring 7 of polycrystalline, and a gate insulating film 4 are successively subjected to a selective etching to provide an opening, and a polycrystalline silicon layer 11 is deposited in the opening. The silicon layer 11 is brought into contact with the gate electrode wiring 7 at a part of its side face and electrically connected with it to enable the gate electrode wiring 7 to be electrically connected to the N-type source/drain region 8b. As mentioned above, an opening is provided to the interlaminar insulating film 10 and the gate insulating film 4, and a conductive material is buried in the opening, whereby a semiconductor integrated circuit of this design is protected against etching at the patterning of a gate electrode and consequently prevented from deteriorating in quality and reliability.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a MOS type semiconductor integrated circuit.

[Conventional technology]

Conventionally, when electrically connecting a gate electrode wiring of a MOS type semiconductor integrated circuit and a diffusion layer provided on a semiconductor substrate, for example, a gate electrode wiring made of N-type polycrystalline silicon and an N-type diffusion layer are connected. In this case, an opening is formed in the insulating film on the N-type diffusion layer, a polycrystalline silicon layer is deposited, the polycrystalline silicon layer is made N-type by phosphorus diffusion, etc., and then patterned to form a gate electrode wiring. was.

[Problem to be solved by the invention]

The conventional method of connecting the gate electrode wiring and the N-type diffusion layer described above is called a buried contact method. In this conventional buried contact method, a gate electrode wiring is formed inside an opening provided on an N-type diffusion layer, so when patterning a polycrystalline silicon layer that will become a gate electrode wiring by a dry etching method, this dry etching method is used. A silicon substrate, which is sometimes used as a semiconductor substrate, is also etched at the same time, and an opening on the N-type diffusion layer that is not covered with the gate electrode wiring is etched. For this reason, part of the N-type diffusion layer is lost, and the junction leakage current of the N-type diffusion layer increases.
There is a drawback that the shape of the glabellar insulating film deposited after the formation of the gate electrode wiring is extremely deteriorated at the opening etched during the dry etching.

[Means to solve the problem]

The present invention provides a MOS type semiconductor integrated circuit in which at least two MOS transistors are formed on a semiconductor substrate and whose surface is covered with an insulating film, in which the insulating film is provided on the source/drain region of one MOS transistor. A conductive layer that fills the opening and electrically connects the gate electrode wiring of the other MOS transistor on its side surfaces.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention.

A P-type head region that will later become a channel stopper is formed on a P-type silicon substrate 1 with a specific resistance of 0.01 Ω・m, and a P-type channel stopper 2 and a field with a thickness of 500 nm are formed using a normal local oxidation method. An oxide film 3 and gate oxide films 4 and 5 having a thickness of 25 Ωm are formed. Deposit a polycrystalline silicon layer and selectively etch it using photolithography to form the gate electrode! Form i6.7. Ion implantation is performed using the gate electrode wirings 6 and 7 as a mask to form N-type source r-drain regions 8a, 8b, 9a, and 9b having a layer resistance of 50 Ω/hole.

A glabellar insulating film 10 with a thickness of 500 nm is deposited by CVD.

Next, the glabella insulating film 10 on the source/drain region 8b
, polycrystalline silicon gate electrode wiring 7, gate insulating film 4
A 1.times.1.5 .mu.m.sup.2 opening is formed by sequentially selectively etching the layers, and a polycrystalline silicon layer 11 is deposited therein to a thickness of 400 nm. This polycrystalline silicon layer 11 covers the gate electrode wiring 7
The gate electrode wiring 7 and the N-type source train region 8b are electrically connected to each other at a part of the side surface thereof, thereby electrically connecting the gate electrode wiring 7 and the N-type source train region 8b. In this way, the source/drain region and the gate electrode wiring are connected by forming an opening in the glabella insulating film and the gate oxide film, burying a conductive material in the opening, and connecting the side surface of the opening with the side surface of the gate electrode wiring. This is a feature of the present invention.

By creating an opening in the glabella insulating film and the gate insulating film and burying the conductive material in this way, the gate electrode will not be etched during patterning, thereby preventing quality deterioration and reliability. be able to.

In the above embodiment, polycrystalline silicon was used as the conductive material buried in the opening, but it is clear that a metal material may also be used.

〔Effect of the invention〕

As explained above, in the present invention, since the conductive material is buried in the opening provided in the glabellar insulating film on the semiconductor substrate and connected to the wiring under the glabellar insulating film, the semiconductor substrate is etched during patterning of the gate electrode wiring. Furthermore, when connecting the gate electrode wiring and the diffusion layer formed in the semiconductor substrate, since the opening is filled with a conductive material, planarization can be achieved at the same time.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... P-type channel stopper 3... Field oxide film, 4, 5... Gate oxide film, 6, 7... Gate electrode wiring, 8a, 8b. 9a, 9b...N-type source/drain regions, 10...
- Interlayer insulating film, 11... polycrystalline silicon layer.

Claims (1)

[Claims] In a MOS type semiconductor integrated circuit in which at least two MOS transistors are formed on a semiconductor substrate and the surface is covered with an insulating film, an opening provided in the insulating film over the source/drain region of one MOS transistor; A MOS type semiconductor integrated circuit comprising a conductive layer that fills the opening and electrically connects the gate electrode wiring of the other MOS transistor from side to side.