JPH0410620A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
) is related to a method of manufacturing a semiconductor device using the method.

(Summary of the Invention) The present invention provides a method for manufacturing a semiconductor device, in which an element isolation insulating film and a gate insulating film are selectively formed on the surface of the semiconductor device, and between the element isolation insulating film and the gate insulating film. A first conductive film is formed on the semiconductor substrate on which the buried contact portion is formed, an etching stopper film is formed on the first conductive film so as to overlap at least the gate insulating film, and a second conductive film is formed on the semiconductor substrate.
By forming a conductor film and patterning the first conductor film and the second conductor film to form the gate electrode, the buried contact portion is exposed during etching to form the gate electrode. This prevents the etched semiconductor substrate from being etched.

[Conventional technology]

Buried contact is, for example, MOS static RA
It is used when bringing a gate electrode into contact with a diffusion layer formed in a semiconductor substrate. A conventional method of manufacturing a semiconductor device using this buried contact will be explained with reference to FIG. 5 as follows. That is, as shown in FIG. 5, first, for example, a field 5i02 (silicon dioxide) film 102 for isolation between elements is formed on the surface of a p-type silicon (Si) substrate 101, and then the field is surrounded by a SiO□ film 102. A SiO□ film 103 is formed on the surface of the exposed active region. Next, a part of the gate SiO□ film 103 is removed by etching to form a contact hole BC' for a buried contact. Next, after forming a polycrystalline Si film 104 and a tungsten silicide (WSiX) film 105 on the entire surface, these WSi, film 105, and polycrystalline Si film 104 are etched onto the substrate surface by reactive ion etching (RIE). Etch vertically. As a result, the polycrystalline Si film 104 and the WSiX film 1 are patterned into a predetermined shape.
A gate electrode G' having a polycide structure made of 0.05 is formed.

In addition, in Japanese Patent Application Laid-open No. 62-37967, polycrystalline Si
When making a buried contact with a gate electrode formed by a film, by covering the surface of the gate insulating film in the area other than the area where the contact hole for the buried contact is formed in advance with a polycrystalline Si film, the buried contact can be made. A technique has been disclosed for preventing light etching of a gate insulating film during etching to form a contact hole for a contact.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, as shown in FIG.
When the X film 105 and the polycrystalline Si film 104 are etched by the RIE method, the p-type Si substrate 101 exposed in the buried contact contact hole BC' is etched, and a groove 106 is formed in this portion. . When the groove 106 is formed in this way, junction leakage may occur in the diffusion layer formed in this portion in a later process, or voids may be generated in the groove 106 portion when an insulating film between the eyebrows is formed. This may cause defects.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the semiconductor substrate exposed in the buried contact portion from being etched during etching to form a gate electrode.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, in which an insulating film (2) for isolation between elements is provided on the surface of the semiconductor device.
and a gate insulating film (3) are selectively formed on the semiconductor substrate (1) in which a buried contact portion is formed between the element isolation insulating film (2) and the gate insulating film (3). 1
A conductor film (5) is formed on the first conductor film (5), an etching stopper film (6) is formed on the first conductor film (5) so as to overlap at least the gate insulating film (3), and a second conductor film (8, 9) is formed on the first conductor film (5). ), and the first conductor film (5) and the second conductor film (8, 9
) by patterning the gate electrodes (C,...)
CZ).

[Effect]

According to the method for manufacturing a semiconductor device of the present invention configured as described above, the first conductor film (
5) When etching the second conductive film (8, 9), the etching stops when the etching stopper film (6) is exposed.

As a result, during etching to form a gate electrode, the semiconductor substrate (1
) can be prevented from being etched.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In addition, in all the drawings of the embodiment, the same parts are given the same reference numerals.

FIG. 1A to the first diagram are MO3 according to the first embodiment of the present invention.
A method for manufacturing an LSI will be shown.

In this first embodiment, as shown in FIG. 1A, first, for example, a field Sin and a film 2 are formed on the surface of a p-type Si substrate 1 by a thermal oxidation method to perform element isolation, and then this field A Ga)SiO□ film 3 is formed on the surface of the active region surrounded by the 5iC)2 film 2 by thermal oxidation. Next, a resist pattern 4 having a predetermined shape with an opening corresponding to the buried contact portion is formed by lithography, and then the gate SiO□ film 3 and the field SiOg film 2 are etched using this resist pattern 4 as a mask.

As a result, a contact hole BC for a buried contact is formed.

Next, after removing the resist pattern 4, as shown in FIG.
After forming the polycrystalline Si film 5, for example, phosphorus (P) is added to the polycrystalline Si film 5.
The resistance is lowered by doping with impurities such as by thermal diffusion or ion implantation.

Next, a 5iC)2 film 6 as an etching stopper film is formed on the surface of this polycrystalline Si film 5 by, for example, thermal oxidation. Thereafter, a resist pattern 7 of a predetermined shape is formed on this SiO□ film 6 so as to completely cover the surface of the buried contact portion.

Next, Sing is performed using this resist pattern 7 as a mask.
The film 6 is etched to form this S as shown in FIG. 1C.
The ing film 6 is left in the contact hole BC for buried contact and in its vicinity so as to overlap with the gate 5i02 film 5. Next, for example, a polycrystalline Si film 8 is formed on the entire surface by CVD method, and after doping an impurity such as P into the polycrystalline Si film 8 by thermal diffusion method or ion implantation method to lower the resistance. For example, a WSiX film 9, for example, is formed on this polycrystalline St film by the same CVD method.

Note that it is also possible to use other high melting point metal silicide films instead of this WSiX film 9. After this, W
Resist pattern 1 for forming gate electrode on SiX film 9
form 0.

Next, using this resist pattern 10 as a mask, WSi
After the X film 8 and the polycrystalline Si film 8.5 are sequentially etched by RIE, the resist pattern 10 is removed. As a result, as shown in the first diagram, gate electrodes G, , G, having a polycide structure consisting of the WSiX film 8 and the polycrystalline Si film 8.5 are formed. In this case, during etching by this RIE method, the etching stops when the SiO□ film 6 and the SiO□ film 3 serving as the etching stopper film are exposed. Therefore, there is no possibility that the p-type St substrate 1 will be etched during etching by this RIE method.

Next, using the gate electrodes G+ and G2 as masks, an n-type impurity such as arsenic (As) is ion-implanted into the p-type Si substrate 1 at a high concentration. After this, heat treatment is performed to electrically activate the implanted impurities. As a result, for example, n1 type diffusion layers 11.12 constituting the source region or the drain region are formed in a self-aligned manner with respect to the gate electrode G2.

As described above, according to the first embodiment, the SiO□ film 6 as an etching stopper film is formed on the polycrystalline Si film in the contact hole BC for buried contact and in the vicinity thereof. Since the gate electrodes G+ and Gz are formed in advance so as to overlap with the film 5,
During etching by the RIE method for forming a buried contact, there is no possibility that the p-type Si substrate 1 exposed in the contact hole BC will be etched and a groove will be formed.

FIG. 2A and FIG. 2A are MOs according to a second embodiment of the present invention.
A method for manufacturing 3LSI will be shown.

In this second embodiment, as shown in FIG. 2A, after forming up to the polycrystalline Si film 5 in the same manner as in the first embodiment,
A Si3N4 film 13 as an oxidation-resistant film is formed on this polycrystalline St film by CVD.

Thereafter, a resist pattern 14 having a predetermined shape is formed on the Si3N4 film 13, with a portion corresponding to the buried contact portion being open.

Next, using this resist pattern 14 as a mask, 5i3
After removing the Si3N4 film 13 at the helirad contact portion by etching the Na film 13, the resist pattern 14 is removed. Thereafter, the portions of the polycrystalline Si film 5 that are not covered with the Si3N4 film 13 are thermally oxidized to form a Si film as an etching stopper film, as shown in FIG. 2B.
NG film 6 is formed.

Next, after removing the 5i3Na film 13 by etching, the first
The steps following the formation of the polycrystalline Si film 8 in the example are carried out to complete the desired MO3LS.

As described above, according to the second embodiment, similarly to the first embodiment, the contact hole BC for buried contact
A StO□ film 6 as an etching stopper film is deposited on the polycrystalline St film 5 in the area and its vicinity.
□Since it is formed in advance so as to overlap with the film 5, the p-type Si substrate 1 exposed for forming the contact hole for the buried contact is etched during the RIE etching to form the gate electrodes G, G2. There is no risk of grooves being formed.

The methods according to the first and second embodiments described above are suitable for application, for example, when making a buried contact of the gate electrode of a MOS transistor in a MOS static RAM.

Incidentally, in a semiconductor device, for example, aluminum (AI) wiring is sometimes brought into contact with an n+ type diffusion layer and a p-well at the same time. Specifically, for example, n+
This is a case where both the type diffusion layer and the p-well are fixed at ground potential. In such a case, conventionally, a contact hole for contacting the A1 wiring with the n-type diffusion layer and a contact hole for contacting the A1 wiring with the p-well were formed separately. For this reason,
Therefore, the area of the contact portion had to be increased accordingly. Next, a method for solving this problem will be described with reference to FIGS. 3A to 3.

That is, in this example, as shown in FIG. 3A, a P well 22 is first formed in, for example, an n-type Si substrate 21, and then a field 5iOz film 23 for isolation between elements is formed on the surface of this P well 22. and further this field 5iO
For example, an n1 type diffusion layer 24 is formed in the active region surrounded by the Z film 23.

Next, as shown in FIG. 3B, after forming an interlayer insulating film 25 over the entire surface, a resist pattern 26 for forming contact holes is formed on this interlayer insulating film 25 by lithography.

Next, using this resist pattern 26 as a mask, the interlayer insulating film 25 and P well 22 are etched in a direction perpendicular to the substrate surface by, for example, RIE.

As a result, a contact hole C reaching into the p-well 22 is formed as shown in FIG. 3C.

Next, a p-type impurity such as boron (B) is ion-implanted into the p-well 22 through this contact hole C at a high concentration. As a result, this contact hole C
For example, a p+ type diffusion layer 27 is formed in the p-well 22 at the bottom of the p-well 22 .

Next, after removing the resist pattern 26, a film is formed on the entire surface by sputtering, for example, and this film is patterned into a predetermined shape by etching to form the AI wiring 28 as shown in the third diagram. Form. In this case, the old wiring 28 contacts the n-type diffusion layer 24 at the side wall of the contact hole C, and at the same time contacts the p'''' type diffusion layer 27 at the bottom of the contact hole C. There is. A plan view of this state is shown in FIG. The third diagram is a sectional view taken along the line ■-■ in FIG. 4.

As described above, according to this example, the A1 wiring 28 can be brought into contact with the n+ type diffusion layer 24 and the p type diffusion layer 27 at the same time with only one contact hole C, so the area of the contact portion is This will be half of what it used to be. This is advantageous in increasing the degree of integration of semiconductor devices.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the first and second embodiments described above,
Although the SiO□ film 6 as an etching stopper film is formed by a thermal oxidation method, this Sing film 6 can also be formed by, for example, a CVD method. Further, it is also possible to use a material other than the 5i02 film 6 as the etching resist film.

Furthermore, in the first and second embodiments described above, the case where the gate electrodes G, , G2 are formed of a polycide film is explained, but these gate electrodes G, , G
The present invention can also be applied to the case where 2 is formed of, for example, a polycrystalline Si film.

〔Effect of the invention〕

As explained above, according to the present invention, since the etching stopper film is formed on the first conductor film so as to overlap with at least the gate insulating film, the etching stopper film is used during etching to form the gate electrode. Etching stops when the film is exposed. This can prevent the semiconductor substrate exposed in the buried contact portion from being etched during etching to form the gate electrode.

[Brief explanation of drawings]

FIG. 1A to the first diagram are MO3 according to the first embodiment of the present invention.
FIGS. 2A and 2B are cross-sectional views for explaining the LSI manufacturing method step by step.
3A to 3 are cross-sectional views for explaining the method for manufacturing an LSI in the order of steps. , FIG. 4 is a plan view corresponding to FIG. 3, and FIG. 5 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device using buried contacts. Explanation of main symbols in the drawings Lap type Si substrate, 2: Field SiO□ film, 3:
Gate SiO□ film, BC: contact hole for buried contact, 6: 5iOz film, 5.8: polycrystalline Si film, 9: WSiX film, GI. G2: Gate electrode. Agent: Patent Attorney Masato Sugiura

Claims (2)

[Claims] (1) A semiconductor substrate on which an insulating film for element isolation and a gate insulating film are selectively formed, and a buried contact portion is formed between the insulating film for element isolation and the gate insulating film. forming a first conductor film on the first conductor film, forming an etching stopper film on the first conductor film so as to overlap at least the gate insulating film, forming a second conductor film, and forming the first conductor film on the first conductor film; A method of manufacturing a semiconductor device, characterized in that a gate electrode is formed by patterning the second conductor film. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the etching stopper film is a silicon dioxide film.