JPH0217343Y2 - - Google Patents
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- Publication number
- JPH0217343Y2 JPH0217343Y2 JP1983005540U JP554083U JPH0217343Y2 JP H0217343 Y2 JPH0217343 Y2 JP H0217343Y2 JP 1983005540 U JP1983005540 U JP 1983005540U JP 554083 U JP554083 U JP 554083U JP H0217343 Y2 JPH0217343 Y2 JP H0217343Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- circuit
- supply circuits
- output line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Measurement Of Current Or Voltage (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Tests Of Electronic Circuits (AREA)
Description
【考案の詳細な説明】
技術分野
本考案はデータレコーダ等の電気回路装置のチ
エツク回路に関するものである。[Detailed Description of the Invention] Technical Field The present invention relates to a check circuit for an electric circuit device such as a data recorder.
従来技術
データレコーダの電源、サーボ回路、消去機
能、各チヤンネルの記録再生増幅器等の良否を、
使用前にチエツクすることは既に行われている。
この種のチエツクは、セルフ・テスト又はセル
フ・チエツクと呼ばれ、チエツク内容に対応した
電圧をA/D変換(アナログ・デジタル変換)し
た後に、マイクロプロセツサ等で正常電圧範囲の
データと比較することによつて行われる。ところ
で、一般的なデータレコーダは例えば+15V,+
9.5V,+5V,+6V,−6V等の複数の電源回路を有
し、且つ多チヤンネル構成であるので、チヤツク
項目が多くなり、必然的にチヤツク回路が複雑に
なつた。Conventional technology Checks the quality of the data recorder's power supply, servo circuit, erase function, recording/reproducing amplifier for each channel, etc.
Checking before use is already done.
This type of check is called a self-test or self-check, and after performing A/D conversion (analog-to-digital conversion) of the voltage corresponding to the content of the check, it is compared with data in the normal voltage range using a microprocessor, etc. It is done by certain things. By the way, general data recorders, for example, +15V, +
Since it has multiple power supply circuits such as 9.5V, +5V, +6V, -6V, etc., and has a multi-channel configuration, the number of check items increases, and the check circuit inevitably becomes complicated.
考案の目的
そこで、本考案の目的は簡略化されたチエツク
回路を提供することにある。Purpose of the invention Therefore, the purpose of the present invention is to provide a simplified check circuit.
考案の構成
上記目的を達成するための本考案は、実施例を
示す図面の符号を参照して説明すると、異なる電
圧を供給するための複数の電源回路を有する電気
回路装置の前記複数の電源回路をチエツクする回
路であつて、前記複数の電源回路の電圧を夫々検
出するために前記複数の電源回路に夫々接続され
ている複数の電圧検出ラインA,B,C,D,E
と、前記複数の電圧検出ラインA,B,C,D,
Eに夫々直列に接続され且つ所定の重みが付けら
れている複数の抵抗R1,R2,R3,R4,R5と、前
記複数の抵抗R1,R2,R3,R4,R5の出力端子に
共通に接続された共通出力ラインFと、前記複数
の抵抗R1,R2,R3,R4,R5を夫々流れる電流の
合計に対応した電圧を前記共通出力ラインFに得
るために前記共通出力ラインFとグランドとの間
に接続された共通の抵抗Rzと、前記共通出力ラ
インFの電圧の大小に基づいて前記複数の電源回
路の良否を判定する判定回路22とを有し、且つ
前記複数の抵抗R1,R2,R3,R4,R5の重みが、
前記複数の電源回路の中の任意の1つの電源電圧
が許容範囲外になつた時に前記共通出力ラインF
の電圧が所定範囲外の値になるように設定されて
いることを特徴とする電気回路装置のチエツク回
路に係わるものである。Structure of the Invention To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments. a plurality of voltage detection lines A, B, C, D, and E connected to the plurality of power supply circuits to respectively detect the voltages of the plurality of power supply circuits;
and the plurality of voltage detection lines A, B, C, D,
A plurality of resistors R 1 , R 2 , R 3 , R 4 , R 5 each connected in series with E and given a predetermined weight, and the plurality of resistors R 1 , R 2 , R 3 , R 4 , R5 , and a voltage corresponding to the sum of the currents flowing through each of the plurality of resistors R1 , R2 , R3 , R4 , and R5 . Judgment for determining the quality of the plurality of power supply circuits based on a common resistor Rz connected between the common output line F and the ground to obtain a voltage on the line F, and the magnitude of the voltage of the common output line F. circuit 22, and the weights of the plurality of resistors R 1 , R 2 , R 3 , R 4 , R 5 are
When the power supply voltage of any one of the plurality of power supply circuits is out of the permissible range, the common output line F
The present invention relates to a check circuit of an electric circuit device characterized in that the voltage of the circuit is set to a value outside a predetermined range.
考案の作用効果
上記考案によれば、共通の抵抗Rzと重みが付
けられた複数の抵抗R1〜R5との組み合せ、共通
の抵抗Rzに流れる合計電流に基づいて電源回路
の異常を判定する。従つて、複数の電源回路に独
立に判定回路を設けることが不要になり、チエツ
ク回路の構成を簡単にすることが出来る。Effects of the invention According to the above invention, abnormalities in the power supply circuit can be detected based on the combination of a common resistance R z and a plurality of weighted resistances R 1 to R 5 and the total current flowing through the common resistance R z . judge. Therefore, it is not necessary to provide independent determination circuits for a plurality of power supply circuits, and the configuration of the check circuit can be simplified.
実施例
次に、第1図及び第2図を参照して本考案の実
施例に係わるチエツク回路を有するデータレコー
ダについて述べる。Embodiment Next, a data recorder having a check circuit according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.
第1図に於いて、1はデータレコーダ本体を原
理的に示すものであり、記録入力端子2、記録回
路3、記録ヘツド4、再生ヘツド5、再生回路
6、再生出力端子7、消去回路8、消去ヘツド
9、磁気テープ10、一対のリール11,12、
キヤプスタン13、ピンチローラ14、サーボ回
路15等を含んでいる。尚記録回路3はA/D変
換器、メモリ、増幅器等を含み、再生回路6はメ
モリ、A/D変換器、増幅器等を含む。また各部
を動作させるために、+15V,+9.5V,+5V,+
6V,−6V、の電源(図示せず)を含む。 In FIG. 1, numeral 1 indicates the main body of the data recorder in principle, and it includes a recording input terminal 2, a recording circuit 3, a recording head 4, a reproduction head 5, a reproduction circuit 6, a reproduction output terminal 7, and an erasing circuit 8. , an erasing head 9, a magnetic tape 10, a pair of reels 11 and 12,
It includes a capstan 13, a pinch roller 14, a servo circuit 15, and the like. Note that the recording circuit 3 includes an A/D converter, a memory, an amplifier, etc., and the reproducing circuit 6 includes a memory, an A/D converter, an amplifier, etc. In addition, in order to operate each part, +15V, +9.5V, +5V, +
Includes 6V and -6V power supplies (not shown).
このデータレコーダ1のセルフ・チエツク回路
は、電源電圧検出回路16と、サーボ電圧検出回
路17と、消去電流検出回路18と、増幅器出力
検出回路19と、各検出回路16〜19の出力を
順次に選択する入力切換器即ちマルチプレクサ2
0と、このマルチプレクサ20の出力をアナロ
グ・デジタル変換するA/D変換器21と、A/
D変換器21の出力と基準とを比較して各チエツ
ク項目の良否を判定するためのマイクロプロセツ
サから成る判定回路22と、判定回路22の結果
を表示する表示器23とから成る。 The self-check circuit of this data recorder 1 sequentially detects the outputs of a power supply voltage detection circuit 16, a servo voltage detection circuit 17, an erase current detection circuit 18, an amplifier output detection circuit 19, and each detection circuit 16 to 19. Input switch to select, i.e. multiplexer 2
0, an A/D converter 21 that converts the output of the multiplexer 20 from analog to digital, and an A/D converter 21 that converts the output of the multiplexer 20 from analog to digital.
It is comprised of a determination circuit 22 comprising a microprocessor for comparing the output of the D converter 21 with a reference to determine the acceptability of each check item, and a display 23 for displaying the results of the determination circuit 22.
電源電圧検出回路16は、データレコーダ1の
複数の電源電圧を夫々検出するために各電源回路
に接続される第1〜第5の電圧検出ラインA,
B,C,D,Eと、これ等の検出ラインA〜Eに
夫々接続され且つ所定の重みが付けられている第
1〜第5の抵抗R1,R2,R3,R4,R5と、各抵抗
R1〜R5の共通出力ラインF、この共通出力ライ
ンFとグランドとの間に接続された抵抗Rzとか
ら成る。そして、この実施例では第1の検出ライ
ンAが第1の電圧V1(+15V)の電源回路に接続
され、以下同様に第2、第3、第4及び第5の検
出ラインB,C,D,Eが第2の電圧V2(+
9.5V)の電源、第3の電圧V3(+5V)の電源、
第4の電圧V4(+6V)の電源、第5の電圧V5(−
6V)の電源に夫々接続されている。また第1の
抵抗R1は75kΩ、第2の抵抗R2は30kΩ、第3の
抵抗R3は8.2kΩ、第4の抵抗R4は12kΩ、第5の
抵抗R5は16kΩ、出力レベル設定抵抗Rzは1kΩに
設定されている。 The power supply voltage detection circuit 16 includes first to fifth voltage detection lines A, which are connected to each power supply circuit in order to detect a plurality of power supply voltages of the data recorder 1, respectively.
B, C, D, E, and first to fifth resistors R 1 , R 2 , R 3 , R 4 , R connected to these detection lines A to E, respectively, and given predetermined weights. 5 and each resistor
It consists of a common output line F of R 1 to R 5 and a resistor R z connected between this common output line F and the ground. In this embodiment, the first detection line A is connected to the power supply circuit of the first voltage V 1 (+15V), and the second, third, fourth and fifth detection lines B, C, D and E are the second voltage V 2 (+
9.5V) power supply, a third voltage V 3 (+5V) power supply,
The power supply of the fourth voltage V 4 (+6V), the fifth voltage V 5 (−
6V) power supply. Also, the first resistor R 1 is 75 kΩ, the second resistor R 2 is 30 kΩ, the third resistor R 3 is 8.2 kΩ, the fourth resistor R 4 is 12 kΩ, and the fifth resistor R 5 is 16 kΩ. Output level setting Resistor Rz is set to 1kΩ.
今、各抵抗R1〜R5を通つてグランドに流れる
電流I1〜I5、また抵抗Rzに流れる合成電流をIと
すれば、
V0=RzI
I=I1+I2+I3+I4+I5
I1=V1−V0/R1、I2=V2−V0/R2、
I3=V3−V0/R3、I4=V4−V0/R4、
I5=V5−V0/R5
の関係が成立するので、出力電圧V0は次式で示
される。 Now, if the currents I 1 to I 5 that flow to the ground through each of the resistors R 1 to R 5 and the combined current that flows to the resistor R z are I, then V 0 = R z I I = I 1 + I 2 + I 3 +I 4 +I 5 I 1 =V 1 −V 0 /R 1 , I 2 =V 2 −V 0 /R 2 , I 3 =V 3 −V 0 /R 3 , I 4 =V 4 −V 0 /R 4 , I5 = V5 - V0 / R5 , so the output voltage V0 is expressed by the following equation.
V0=(V1/R1+V2/R2+V3/R3+V4/R4+V5/R5)/
(1/Rz+1/R1+1/R2+1/R3+1/R4+1/R5)
各検出ラインA〜Eの電圧V1〜V5が標準値の
場合の出力電圧V0を求めると、V0≒0.952Vとな
る。そこで、本実施例では、この出力電圧V0が
マルチプレクサ20を通つてA/D変換器21に
入力し、ここでデジタル信号に変換されてマイク
ロプロセツサで構成された判定回路22に入力
し、判定回路22に内蔵されたメモリに予め書き
込まれている0.9V及び1.0Vの基準データとデジ
タル比較され、出力電圧V0が0.9〜1.0Vの範囲内
の場合には電源良の判定出力が表示器23に送ら
れ、これが表示される。一方、出力電圧V0が
0.9V未満の場合及び1.0Vを越えた場合は電源不
良の判定出力が表示器23に送られる。 V 0 = (V 1 /R 1 +V 2 /R 2 +V 3 /R 3 +V 4 /R 4 +V 5 /R 5 ) /
(1/R z +1/R 1 +1/R 2 +1/R 3 +1/R 4 +1/R 5 )
When the output voltage V 0 is determined when the voltages V 1 to V 5 of each detection line A to E are standard values, V 0 is approximately 0.952V. Therefore, in this embodiment, this output voltage V 0 is input to the A/D converter 21 through the multiplexer 20, where it is converted into a digital signal and input to the determination circuit 22 composed of a microprocessor. It is digitally compared with the reference data of 0.9V and 1.0V written in advance in the memory built into the judgment circuit 22, and if the output voltage V0 is within the range of 0.9 to 1.0V, a judgment output indicating that the power supply is good is displayed. It is sent to the device 23 and displayed. On the other hand, the output voltage V 0
If the voltage is less than 0.9V or exceeds 1.0V, a power supply failure judgment output is sent to the display 23.
ところが、第1の電圧V1が−30%変動すると
出力電圧V0は0.90640V、+30%変動するとV0は
1.01291V、第2の電圧V2が−20%変動するとV0
は0.90387V、+20%変動するとV0は1.00023V、第
3の電圧V3が−10%変動するとV0は0.90566V、+
10%変動するとV0は0.99844V、第4の電圧V4が
−15%変動するとV0は0.89500V、+15%変動する
とV0は1.00911V、第5の電圧V5が−15%変動す
るとV0は0.99484V、+15%変動するとV0は
0.90926Vとなる。従つて、第1の電圧V1が略−
30%〜+30%の範囲、第2の電圧V2が略−20%
〜+20%の範囲、第3の電圧V3が略−10%〜+
10%の範囲、第4の電圧V4が略−15%〜+15%
の範囲、第5の電圧V5が略−15%〜+15%の範
囲を越えるように変化すると、電源不良の判定結
果が得られる。尚一方の電源の電圧が増大し、同
時に他方の電源の電圧が減少すれば、打ち消し合
が生じて出力電圧V0が0.9〜1.0Vから外れるよう
に変化しない場合も生じる。しかし、2つの電源
回路が同時に異常になる確率及び一方の電圧が増
大し他方の電圧が減少するような異常が同時に生
じる確率は極めて少ないので、実際上殆んど問題
がない。 However, when the first voltage V 1 fluctuates by -30%, the output voltage V 0 becomes 0.90640V, and when the first voltage V 1 fluctuates by +30%, V 0 becomes
1.01291V, when the second voltage V 2 fluctuates by -20%, V 0
is 0.90387V, when the third voltage V 3 changes by -10%, V 0 is 1.00023V, when the third voltage V 3 changes by -10%, V 0 is 0.90566V, +
When the fourth voltage V 4 changes by -15%, V 0 becomes 0.89500 V. When the fourth voltage V 4 changes by -15%, V 0 becomes 0.89500 V. When the fifth voltage V 4 changes by -15%, V 0 becomes 1.00911 V. When the fifth voltage V 5 changes by -15%, V 0 becomes 0.89500 V. V 0 is 0.99484V, when it fluctuates by +15%, V 0 becomes
It becomes 0.90926V. Therefore, the first voltage V 1 is approximately −
Range of 30% to +30%, second voltage V 2 approximately -20%
~ +20% range, the third voltage V 3 is approximately -10% ~ +
10% range, the fourth voltage V 4 is approximately -15% to +15%
If the fifth voltage V5 changes beyond the range of -15% to +15%, a determination result of a power supply failure is obtained. Note that if the voltage of one power source increases and the voltage of the other power source decreases at the same time, cancellation may occur and the output voltage V 0 may not change to deviate from 0.9 to 1.0V. However, since the probability that two power supply circuits become abnormal at the same time and the probability that abnormalities such as one voltage increasing and the other voltage decreasing simultaneously are extremely small, there is almost no problem in practice.
この実施例では第1〜第5の電圧V1〜V5の正
常範囲の割合が全部同一にならないように第1〜
第5の抵抗R1〜R5に重みがつけられているが、
正常範囲が同一になるように抵抗R1〜R5の重み
を設定してもよい。また重要度に応じて重みを変
えてもよい。 In this embodiment, the proportions of the normal ranges of the first to fifth voltages V 1 to V 5 are not all the same.
Although weights are attached to the fifth resistors R 1 to R 5 ,
The weights of the resistances R 1 to R 5 may be set so that the normal ranges are the same. Further, the weight may be changed depending on the degree of importance.
このデータレコーダはサーボ機能、消去機能、
増幅機能のチエツクも可能であり、使用に先立つ
てこれらのチエツクも行われる。即ち、これ等に
対応する電圧がマルチプレクサ20で選択されて
A/D変換器21を通して判定回路22に送られ
ここでメモリに記憶されている基準データと比較
され、その良否が判定される。尚、第1図ではデ
ータレコーダの1チヤンネル分のみが示されてい
るが、実際には多チヤンネル構成であるので、各
チヤンネルのチエツクを行う。 This data recorder has servo function, erase function,
It is also possible to check the amplification function, and these checks are also performed prior to use. That is, the voltages corresponding to these are selected by the multiplexer 20 and sent to the determination circuit 22 through the A/D converter 21, where they are compared with reference data stored in the memory to determine whether or not they are acceptable. Although only one channel of the data recorder is shown in FIG. 1, since the data recorder actually has a multi-channel configuration, each channel is checked.
判定回路22は原理的には第2図に示す如く基
準データを記憶するメモリ等から成る基準回路2
4とこの基準回路24から得られる基準データと
A/D変換器21から送られる例えば出力電圧
V0のようなデータとを比較する比較回路25と
から成る。 The determination circuit 22 is, in principle, a reference circuit 2 consisting of a memory or the like that stores reference data as shown in FIG.
4, the reference data obtained from this reference circuit 24 and, for example, the output voltage sent from the A/D converter 21.
It consists of a comparison circuit 25 that compares data such as V 0 with data such as V 0 .
上述から明らかなように本実施例によれば、電
圧V1〜V5を得るための複数の電源に対応して複
数のチエツク回路を設けなくとも、電源の異常を
検出することが出来る。従つて、マルチプレクサ
20及び判定回路22の構成を簡略化することが
出来る。また、判定回路22を構成するマイクロ
プロセツサのソフトの単純化が可能になる。 As is clear from the above, according to this embodiment, it is possible to detect an abnormality in the power supply without providing a plurality of check circuits corresponding to the plurality of power supplies for obtaining the voltages V1 to V5 . Therefore, the configurations of the multiplexer 20 and the determination circuit 22 can be simplified. Furthermore, the software of the microprocessor constituting the determination circuit 22 can be simplified.
変形例
電源電圧の良否の判定を出力電圧V0と基準電
圧とのアナログ比較で行うようにしてもよい。ま
た抵抗Rzを省いた構成とし、出力ラインFの後
段のインピーダンスを利用してもよい。また、
FM記録のデータレコーダ又はその他の電気回路
装置にも適用可能である。また、マルチプレクサ
20、A/D変換器21、判定回路22をデータ
レコーダ本体1に含まれているマルチプレクサ、
A/D変換器、マイクロプロセツサと兼用するよ
うにしてもよい。Modification The quality of the power supply voltage may be determined by analog comparison between the output voltage V 0 and the reference voltage. Alternatively, the configuration may be such that the resistor Rz is omitted, and the impedance at the latter stage of the output line F may be used. Also,
It is also applicable to FM recording data recorders or other electrical circuit devices. In addition, the multiplexer 20, A/D converter 21, and determination circuit 22 are replaced by a multiplexer included in the data recorder main body 1,
It may also be used as an A/D converter and a microprocessor.
第1図は本考案の実施例に係わるデータレコー
ダを示すブロツク図、第2図は第1図の判定回路
を原理的に示すブロツク図である。
16……電源電圧検出回路、21……A/D変
換器、22……判定回路、23……表示器、A〜
E……電圧検出ライン、F……共通出力ライン、
R1〜R5……重みをつけられた抵抗、V0……出力
電圧。
FIG. 1 is a block diagram showing a data recorder according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the principle of the determination circuit of FIG. 1. 16...Power supply voltage detection circuit, 21...A/D converter, 22...Judgment circuit, 23...Display device, A~
E...Voltage detection line, F...Common output line,
R 1 ~ R 5 ... weighted resistance, V 0 ... output voltage.
Claims (1)
有する電気回路装置の前記複数の電源回路をチエ
ツクする回路であつて、 前記複数の電源回路の電圧を夫々検出するため
に前記複数の電源回路に夫々接続されている複数
の電圧検出ラインA,B,C,D,Eと、 前記複数の電圧検出ラインA,B,C,D,E
に夫々直列に接続され且つ所定の重みが付けられ
ている複数の抵抗R1,R2,R3,R4,R5と、 前記複数の抵抗R1,R2,R3,R4,R5の出力端
子に共通に接続された共通出力ラインFと、 前記複数の抵抗R1,R2,R3,R4,R5を夫々流
れる電流の合計に対応した電圧を前記共通出力ラ
インFに得るために前記共通出力ラインFとグラ
ンドとの間に接続された共通の抵抗Rzと、 前記共通出力ラインFの電圧の大小に基づいて
前記複数の電源回路の良否を判定する判定回路2
2と を有し、且つ前記複数の抵抗R1,R2,R3,R4,
R5の重みが、前記複数の電源回路の中の任意の
1つの電源電圧が許容範囲外になつた時に前記共
通出力ラインFの電圧が所定範囲外の値になるよ
うに設定されていることを特徴とする電気回路装
置のチエツク回路。[Claims for Utility Model Registration] A circuit for checking a plurality of power supply circuits of an electric circuit device having a plurality of power supply circuits for supplying different voltages, the circuit for detecting the voltage of each of the plurality of power supply circuits. a plurality of voltage detection lines A, B, C, D, and E, each of which is connected to the plurality of power supply circuits; and a plurality of voltage detection lines A, B, C, D, and E.
a plurality of resistors R 1 , R 2 , R 3 , R 4 , R 5 each connected in series with a predetermined weight; and a plurality of resistors R 1 , R 2 , R 3 , R 4 , A voltage corresponding to the sum of the currents flowing through the common output line F commonly connected to the output terminal of R 5 and the plurality of resistors R 1 , R 2 , R 3 , R 4 , and R 5 is connected to the common output line F. a common resistor Rz connected between the common output line F and the ground to obtain a voltage of F; and a determination circuit that determines the quality of the plurality of power supply circuits based on the magnitude of the voltage of the common output line F. 2
2, and the plurality of resistors R 1 , R 2 , R 3 , R 4 ,
The weight of R5 is set such that when the power supply voltage of any one of the plurality of power supply circuits falls outside the permissible range, the voltage of the common output line F becomes a value outside a predetermined range. A check circuit for an electric circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP554083U JPS59120482U (en) | 1983-01-19 | 1983-01-19 | Check circuit for electrical circuit equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP554083U JPS59120482U (en) | 1983-01-19 | 1983-01-19 | Check circuit for electrical circuit equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59120482U JPS59120482U (en) | 1984-08-14 |
| JPH0217343Y2 true JPH0217343Y2 (en) | 1990-05-15 |
Family
ID=30137129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP554083U Granted JPS59120482U (en) | 1983-01-19 | 1983-01-19 | Check circuit for electrical circuit equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59120482U (en) |
-
1983
- 1983-01-19 JP JP554083U patent/JPS59120482U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59120482U (en) | 1984-08-14 |
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