JPH02174149A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02174149A
JPH02174149A JP63331760A JP33176088A JPH02174149A JP H02174149 A JPH02174149 A JP H02174149A JP 63331760 A JP63331760 A JP 63331760A JP 33176088 A JP33176088 A JP 33176088A JP H02174149 A JPH02174149 A JP H02174149A
Authority
JP
Japan
Prior art keywords
resin
frame
die frame
die
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63331760A
Other languages
Japanese (ja)
Inventor
Takehiko Matsunaga
松永　毅彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63331760A priority Critical patent/JPH02174149A/en
Publication of JPH02174149A publication Critical patent/JPH02174149A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To avoid concentration of heat in one part and to enhance adhesiveness with reference to a resin by a method wherein a lead frame is connected to a plurality of die frames and peripheral parts of the die frames are bent downward. CONSTITUTION:A die frame 5 on which a gold wire 1, a resin 2, lead frames 3 and a chip 4 are loaded is provided; peripheral parts of the die frame 5 are bent downward; the number of connections between the die frame 5 and the lead frames 3 are increased to four. That is to say, a total of four lead frames out of the lead frames 3 are connected to the inside die frame 5; a diffusion property of heat is made good; a surface area of the individual frames 3 coming into contact with the resin 2 is increased; in addition, a shape of the die frame 5 is treated so as to improve adhesiveness with reference to the resin 2. Thereby, it is possible to avoid concentration of heat in one part and to increase the adhesiveness with reference to the resin.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置のフレームの形状に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a frame of a semiconductor device.

〔従来の技術〕[Conventional technology]

第３図は従来の半導体装置の断面図で、図において、（
１）は金線、（２）は樹脂、（８）はリードフレーム、
（４）はチップ、（５）はチップ（４）を載置するダイ
フレームである。FIG. 3 is a cross-sectional view of a conventional semiconductor device, and in the figure (
1) is gold wire, (2) is resin, (8) is lead frame,
(4) is a chip, and (5) is a die frame on which the chip (4) is placed.

次に動作について説明する。半導体装置はリードフレー
ム（８）、樹脂（２）、チップ（４）等、熱伝導率が違
う材質で作られており、熱の加わる速度が違っている。Next, the operation will be explained. A semiconductor device is made of materials such as a lead frame (8), resin (2), and chip (4) that have different thermal conductivities, and heat is applied at different rates.

１０全体金熱するりフロー半田等ではダイフレーム（５
）が最初に熱せられ１次にその周辺の樹脂（２）の温度
が上がって行き、ダイフレーム（６）と樹脂（２）の密
着性が弱い箇所（ダイフレーム（δ）の内の外部リード
（８）と接続されていない側面）でクラックはく離が発
生していた。10 The entire die frame (5
) is heated first, and then the temperature of the resin (2) around it increases, and the adhesiveness between the die frame (6) and the resin (2) is weak (external leads in the die frame (δ)). Cracks and peeling occurred on the side surface (not connected to (8)).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置は以上の様に構成されていたので、ダ
イフレームと樹脂の密着性が悪く、又熱の放出の点でも
伝導性が悪く、また半田リフロー等の熱をＩＣ全体に加
えた場合、ダイフレームの側面の箇所で樹脂クラックが
起こるなどの問題点があった。Conventional semiconductor devices were constructed as described above, so the adhesion between the die frame and the resin was poor, and the conductivity was also poor in terms of heat release, and when heat was applied to the entire IC during solder reflow etc. However, there were problems such as resin cracks occurring on the side surfaces of the die frame.

この発明は上記のような問題点を解消するためになされ
たもので、熱放散を良くし熱の一部集中を避けると共に
、樹脂との密着性を良くした半導体装置を得る事を目的
とする。This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor device that improves heat dissipation, avoids partial concentration of heat, and improves adhesion to resin. .

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置はダイフレームの周辺の形状
を下側に折り曲げ、又外部リードフレームとの接続本数
を増加させたものである。In the semiconductor device according to the present invention, the shape of the periphery of the die frame is bent downward, and the number of connections to an external lead frame is increased.

〔作用〕[Effect]

この発明におけるリードフレームおよびグイフレームの
形状は熱放散性を良くし、熱の一部集中を避け、又樹脂
との密着性を増大させる事ができる。The shape of the lead frame and goo frame in this invention improves heat dissipation, avoids partial concentration of heat, and increases adhesion to the resin.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図において、（１）は金線、（２）は樹脂、（８）はリ
ードフレーム、（４）はチップ、（６）はチップ（４）
を載置するダイフレームで、ダイフレーム（５）はその
周辺を図示の如く下側に折り曲げられており、ダイフレ
ーム（５）とリードフレーム（８）の接続本数を４本に
増やしである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is gold wire, (2) is resin, (8) is lead frame, (4) is chip, (6) is chip (4)
The periphery of the die frame (5) is bent downward as shown in the figure, and the number of connections between the die frame (5) and the lead frame (8) is increased to four.

次に動作について説明する。リードフレーム（８）の内
、合計４本は内部グイフレーム（５）と接続されており
、熱の放散性を良くし、熱の一部集中を避ける事ができ
る。又、樹脂（２）に接する各フレームの表面積が増え
る為、樹脂（２）との密着性が良くなる。一方、ダイフ
レーム（５）の形状を下側に折シ曲げる事により、樹脂
（２）との密着性を良くする事ができる。Next, the operation will be explained. A total of four of the lead frames (8) are connected to the internal goo frame (5), which improves heat dissipation and prevents partial concentration of heat. Furthermore, since the surface area of each frame in contact with the resin (2) increases, the adhesion with the resin (2) improves. On the other hand, by bending the shape of the die frame (5) downward, it is possible to improve the adhesion with the resin (2).

以上により、リフロー半田等ＩＣ全体を熱す゛る場合に
も熱のダイフレーム（５）への集中を避ける事ができる
。As described above, even when the entire IC is heated by reflow soldering, etc., it is possible to avoid concentration of heat on the die frame (5).

なお、上記実施例ではリードフレーム（８）の内４本を
内部グイフレーム（５）と接続させた場合を示したが、
さらにその本数を増やす事も可能である。In addition, in the above embodiment, four of the lead frames (8) were connected to the internal Gui frame (5), but
It is also possible to further increase the number.

また、ダイフレーム（６）の周辺を下側に折り曲げる事
により、樹脂（２）との間でクラックが起こっても、下
側（熱集中が起こり易い方向にしかクラックが入らず、
チップ（４）、金線（１）を保護する事ができる。In addition, by bending the periphery of the die frame (6) downward, even if a crack occurs between the die frame (6) and the resin (2), the crack will only occur on the lower side (in the direction where heat concentration is likely to occur).
Chip (4) and gold wire (1) can be protected.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、リードフレームを複数
本グイフレームと増加接続させ、又ダイフレームの周辺
を下側に折シ曲げる事により、熱集中を避ける事ができ
、樹脂とのクラックが防止できる効果がある。As described above, according to the present invention, by increasing the number of lead frames connected to a plurality of lead frames and bending the periphery of the die frame downward, heat concentration can be avoided and cracks with the resin can be avoided. It has a preventive effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例による半導体装置を示す断
面図、第２図は第１図のフレームのみの上面図、第３図
は従来の半導体装置を示す断面図である。 図において、（１）は金線、（２）は樹脂、（８）はリ
ードフレーム、（４）はチップ、（６）はダイフレーム
を示す。 なお、図中、同一符号は同一　または相当部分を示す。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a top view of only the frame shown in FIG. 1, and FIG. 3 is a sectional view showing a conventional semiconductor device. In the figure, (1) is a gold wire, (2) is a resin, (8) is a lead frame, (4) is a chip, and (6) is a die frame. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置のダイフレームの端を折り曲げ、外部リード
フレームとの接続本数を増やした事を特徴とする半導体
装置。A semiconductor device characterized in that the end of the die frame of the semiconductor device is bent to increase the number of connections to an external lead frame.
JP63331760A 1988-12-26 1988-12-26 Semiconductor device Pending JPH02174149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63331760A JPH02174149A (en) 1988-12-26 1988-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63331760A JPH02174149A (en) 1988-12-26 1988-12-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02174149A true JPH02174149A (en) 1990-07-05

Family

ID=18247313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63331760A Pending JPH02174149A (en) 1988-12-26 1988-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02174149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019116457A1 (en) * 2017-12-13 2019-06-20 三菱電機株式会社 Semiconductor device and power conversion device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019116457A1 (en) * 2017-12-13 2019-06-20 三菱電機株式会社 Semiconductor device and power conversion device
JPWO2019116457A1 (en) * 2017-12-13 2020-05-28 三菱電機株式会社 Semiconductor device and power converter

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