JPH02174166A - Manufacture of compound semiconductor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (b) Industrial application fields The present invention relates to a method for manufacturing a compound semiconductor.

For more details, see compound semiconductor MIS capable of high-speed operation.
The present invention relates to a type field effect transistor and a manufacturing method thereof.

(b) Conventional technology Elements using compound semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP), which are attracting attention as semiconductors that can replace silicon, are making it difficult to put into practical use high-speed, high-performance semiconductor devices and their integrated circuits. It is expected. M.I.S.
(MeLal-I n5ulator-S emic
An advantage of a Schottky (MES) field effect transistor is that it has a higher driving capability than a Schottky (MES) field effect transistor, and this advantage is more pronounced in enhancement mode transistors.

Conventionally, as a method for manufacturing this type of MIS type field effect transistor, a process example shown in FIG. 2 has been generally used. That is, first, an n-type layer 20 which will become a source/drain part is formed on a semi-insulating substrate 21, and then the n-type layer in the channel region and field part is removed to form a source part 27 and a drain part. 28 (Fig. 2(b)
)) After that, a gate insulating film 22 is deposited. After that, a gate electrode 23 is formed by lithography (see FIG. 2).
c) Next, the gate insulating film 22 directly above the source part 27 and drain part 28 is removed to form a contact 71, and a source electrode 29 and a drain electrode 30 are formed (
It is manufactured by FIG. 2(d)).

(c) Problems to be Solved by the Invention When manufacturing an enhancement mode field effect transistor, a pair of 11
A gate electrode must be placed between the type semiconductor regions so as to be aligned therewith. This is because if there is a horizontal gap between the pair of n-type semiconductor regions and the gate electrode, the channel layer directly under it acts as a resistance even during operation, reducing the operation speed. This is because if there is a large horizontal overlap between the type semiconductor region and the gate electrode, parasitic capacitance will occur there, resulting in a reduction in operating speed.

Therefore, in order to achieve high-speed operation, it is necessary to match the source and drain parts with the gate electrode. However, in the above-mentioned normal mask alignment, there is a limit to the accuracy of alignment, and alignment is particularly difficult for submicron devices.

Attempts have been made to achieve self-alignment using ion implantation, which has been successful in the silicon process.
In compound semiconductors, since the vapor pressure of group V elements is high, there are still technical problems such as incomplete recovery of crystallinity by heat treatment such as annealing after ion implantation.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for manufacturing a compound semiconductor field effect transistor having a self-aligned structure.

(d) Means for Solving the Problems Thus, according to the present invention, a gate electrode is formed in a predetermined region on a compound semiconductor substrate via an insulating layer, and then an insulating layer is formed on the substrate to form a gate electrode and a gate electrode. Covering the surface of the electrode-forming substrate, then removing by etching the covering insulating layer corresponding to the regions where the source and drain regions of the semiconductor substrate are planned to be formed, and forming a remaining side wall made of the insulating layer around the side of the gate electrode. Then, by etching the semiconductor substrate using the sidewalls and the remaining covering insulating layer as a mask, the substrate portion corresponding to the area where the source and drain regions are to be formed is removed, and an n-type semiconductor layer is selected in the etched portion. Provided is a method for manufacturing a compound semiconductor, characterized in that source and drain regions are formed by selectively forming the source and drain regions.

The compound semiconductor substrate in this invention means a substrate in which the element region forming portion is made of a compound semiconductor.

As the compound semiconductor, those known in the art such as InP, GaAs+, and indium gallium arsenide (InC; aAs) can be used as they are.

The material for forming the gate electrode in this invention is as follows:
Molybdenum (MO), ditane ('l'i),
High melting point metals such as tantalum ('1.'a) and tungsten (W), or their solicides, etc. can be used.

In this invention, the gate electrode is formed on the compound semiconductor substrate using a method known in the art.

In the etching of the covering insulating layer of the present invention, a method is used in which the insulating layer portions corresponding to the areas where the source and drain regions are to be formed are removed, and the insulating layer is left as a sidewall around the side of the gate electrode. It will be done.

Examples of such etching methods include performing reactive ion etching under anisotropic etching conditions.

In the present invention, etching the semiconductor substrate using the sidewall as a mask means etching only the semiconductor substrate without etching the insulating film constituting the sidewall. This is determined by the choice of etching solution (etchant). Examples of edgeants that can be used include sulfuric acid, nitric acid, phosphoric acid, and hydrogen bromide. Further, the edging depth at this time is preferably 1,000 to 5,000 people, and preferably about 3,000 people.

In the present invention, an n-type semiconductor thin layer is selectively formed in the etched portion of the semiconductor substrate by the above-described etching, and source and drain regions are formed. The n-type semiconductor thin layer may be made of the same material as the substrate or a different material. Silicon or sulfur is also used as the impurity. The impurity concentration is preferably I x 10'' to I x 10''cm-', more preferably about 3 x 1 OI8CI11-3. As a method for selectively forming the n-type semiconductor thin layer in the etching removed portion, MO
Examples include the CVD method. According to this method, a semiconductor thin layer is epitaxially grown on a semiconductor substrate, but
Only a small amount of amorphous or polycrystalline film is deposited on the insulating film, which allows selective growth in the etched areas.

(E) Function According to this invention, the compound semiconductor substrate's second gate il
Using the Zidewall made of an insulating layer formed around the l-pole side and the insulating layer remaining on the substrate as a mask,
- After etching the semiconductor substrate to remove a predetermined region, an n-type semiconductor thin layer is selectively grown and buried in the removed portion, so that the gate 7tHji and the source and drain regions made of the n-type semiconductor thin layer are self-contained. Consistently formed.

The present invention will be described in detail below with reference to Examples, but the present invention is not limited thereby.

(f) Example FIGS. 1(a) to 1(g) are cross-sectional configuration explanatory diagrams illustrating steps of an example of the method for manufacturing a compound semiconductor of the present invention.

The figure shows an MIS with an indium phosphide (InP) substrate.
A method for manufacturing a type field effect transistor (MisF E 'l') is taken as an example.

First, E CRI) C is placed on a semi-insulating substrate (InP) 1.
The 5ift film I2, which will become the gate insulating film 2, is made by the VD method to 100%
M is deposited and then becomes the gate electrode 3 by sputtering.
O5it thin film 13 was deposited by 3000 people and further PCVD
Deposit 1,000 5iO1 films ■4 using the method (Fig. 1 (a)
)).

Next, by photolithography, the S of the area that will become the gate is
iO! The film 4, the Mo5it film 3.5ift film 2 are removed by reactive etching, leaving only the film 2 (FIG. 1(b)).

At this time, the etching is performed under anisotropic etching conditions so that the pattern is vertical. Next, the entire surface of the substrate is coated with S by the PCVD method.
1000 people deposited iOz@15 (Figure 1 (C)
), this S
In, membrane 15 is removed by reactive ion etching. At this time, if the etching is performed under anisotropic etching conditions, the insulating film 1
At the time when 5 is etched, a zide wall 5 is formed on the side surface of the gate electrode 3 (FIG. 1(d)). Also, at this time, 5iOy@ with a film thickness equivalent to the Sing film 4 remains on the gate electrode 3, and the gate electrode 3 is completely made of Si.
Surrounded by an O2 film.

Next, the nP substrate 1 is etched to a depth of 3000 nm using the insulating film 4, the wall 5, and the field insulating film 6 as masks (FIG. 1(e)). At this time, in order to facilitate selective growth as described later, a hydrogen bromide-based edgeant was used that caused less side etching and had a smooth etched shape.

Next, after treating with dilute hydrochloric acid to remove the natural oxide film in the etching removed portions 17 and 18, n is etched by MOCVD.
A type 1nP layer is selectively epitaxially grown on the etched portions 17 and 18 to form a source portion 7 and a drain portion 8 (FIG. 1(r)). During epitaxial growth, the gate electrode 3 is surrounded by the 5ift film 4 and the zide wall 5, so that it does not contaminate the MOCVD apparatus. Also, during epitaxial growth, amorphous or polycrystalline 1nP is deposited several tens of times thicker on the 5iOz film 4, Zydo A-ru 5, and field insulating film 6, so the entire surface of the substrate is lightly etched with a hydrogen bromide-based edger. and removed this.

Finally, Au/Ni/AuGe was evaporated to form a source electrode 9 and a drain electrode IO by a lift-off method, and then annealing was performed at 300° C. for 30 minutes in a hydrogen atmosphere to form [nP MI SFE'I''. completed.

- As mentioned above, in this embodiment, the substrate was etched using the Zide wall formed on the side periphery of the gate 7 [pole] as a mask, and the source and drain were buried in this region. The capacitance between (drain) and gate was reduced, allowing high-speed operation of the transistor.

(G) Effects of the Invention According to this invention, the semiconductor substrate is etched using the zide wall formed on the side surface of the gate electrode as a mask, and an n-type layer is selectively epitaxially grown in the etched region. Since the gate electrode and the source/drain can be formed in a self-aligning manner, there is no horizontal gap or overlap between the gate electrode and the source/drain, thus reducing the resistance of the channel part and the capacitance between the source (drain) and gate. can do. the result,
It becomes effective as a high-speed operation element and can contribute greatly to industry.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional schematic diagram showing an example of the compound semiconductor manufacturing method of the present invention, and FIG. 2 is a cross-sectional diagram explaining a conventional MISFET manufacturing method. It is a process explanatory diagram. 1.21...Semi-insulating 1nP substrate, 20...
・N-type 1nP thin layer, 2, 12.22...Sin, film (gate insulating film), 3, 13--...MoS it (gate electrode)
, 23...Al2 (gate electrode), 4.14
...SiO2 film, 5...5idt film (Zyde wall), 6...5iOz film (field insulating film), 15...5iot film, 17
．． 18...Etching region, 7.27--n type 1nP (source), 8.28...n type 1nP (drain), 9, 2
9--...-Au/Ni/AuGe (source electrode)
, 10, 30-=Au/Ni/AuGe (drain electrode). Figure 2

Claims (1)

[Claims] 1. After forming a gate electrode in a predetermined region on a compound semiconductor substrate via an insulating layer, an insulating layer is formed on the substrate to cover the gate electrode and the surface of the substrate on which the electrode is formed, and then a source of the semiconductor substrate is formed. Then, the covering insulating layer corresponding to the region where the drain region is to be formed is removed by etching, and a sidewall made of the insulating layer is left on the side periphery of the gate electrode, and then, using the sidewall and the remaining covering insulating layer as a mask, the A semiconductor substrate is etched to remove a portion of the substrate corresponding to an area where the source and drain regions are to be formed, and an n-type semiconductor layer is selectively formed in the etched removed portion to form the source and drain regions. A method for manufacturing a compound semiconductor.