JPH0217544A - Information processor - Google Patents

Abstract

PURPOSE:To save plural error addresses at the time of the occurrence of a bus error cycle by storing the address of error, which occurs at the time of reading an external storage, in a private storage means to perform interrupt handling. CONSTITUTION:The write address on an internal bus 11 is stored in a register 1 designated by a select signal in accordance with execution of a micro instruction. Write data is stored in a register 7 similarly to start a write cycle. When a bus cycle error occurs to give an error signal to a control logic 23, a signal EAR is given to an error address storage register EAR 9 from the control logic 23. Then, the error address is copied in the EAR 9, and an interrupt signal is outputted to a micro instruction control part simultaneously. After the interrupt signal is outputted, the error address stored in the EAR 9 is pushed to a stack through the internal bus 11.

Description

[Detailed Description of the Invention] [Objective of the Invention 1 (Field of Industrial Application) This invention relates to information processing that saves multiple error addresses when an error occurs during execution of a bus cycle for prefetching memory operands. Regarding equipment.

(Prior Art) Some information processing apparatuses prefetch memory operands using briefetched instructions in order to improve processing speed.

FIG. 2 is a diagram illustrating a main part configuration for performing a memory operand read operation in J3 in such an information processing apparatus.

In the information processing device shown in FIG. 2, a memory address corresponding to a memory operand to be read from external storage (not shown) is stored in a register in address storage register group (AP) 1 by a microinstruction. be done. The memory address stored in this register group 1 is transferred to a memory address register (MAR) 5 by an AP select signal given from the control logic 3. The transferred memory address is latched into the MAR 5 by an address latch signal applied from the control logic 3, and then applied to external storage.

Thereby, the operand data read from the external storage is outputted from the control logic 3 in synchronization with the pi-cycle end signal given to the control logic 3 from the outside.
The data is stored in the register in the data storage register group 7 specified by the select signal. In this manner, the memory operand data read operation is performed.

In such a read operation, a bus cycle error may occur. This bus cycle error is caused by information processing S! This is one of the errors that occur when the device accesses external storage.

A bus cycle error signal is output when an error is detected by the parity error check circuit in external storage, or when an attempt is made to access the W4 area of external storage that is not allowed to be accessed. Occurs due to

When a bus cycle error occurs, in order to handle it through interrupt processing, the information processing device must save (evacuate and hold) the address that caused the bus cycle error and pass it to the interrupt handler as interrupt information. . Therefore, the address that caused the bus cycle error is given and stored on the stack.

Therefore, in the configuration shown in FIG. 2, if a bus cycle error occurs when reading a memory operand, a bus cycle error signal is applied to the control logic 3 from the outside. In addition, E synchronized with the bus cycle error signal
The ARt left signal is applied from the 11i17 control logic 3 to the error address storage register 9. As a result, a bus cycle error is generated, and the address stored in MAR5 is given to and stored in the error address storage register 9 specified by the EAR select signal. That is, the address stored in MAR5 is copied to error address storage register 9 as an error address. The copied error address is sent to the EA by the interrupt processing microprogram activated by the interrupt signal output from the control logic 3.
It is read from R9 and sent to the stack (
(not shown).

(Problems to be Solved by the Invention) In the information processing apparatus that pre-reads operand data as described above, the read operand data is not necessarily used. Sometimes it is not used. Therefore, no interrupt signal is output until the read operand data is actually used. That is, at the stage of pre-reading, a pruning signal is not output even if it is a bus cycle error, but at the stage of actual use, an interrupt signal is output to respond to the bus cycle error. therefore,
It is also necessary to hold error addresses equal to the number of read-aheads.

Therefore, in the information processing apparatus shown in FIG. 2, the error address storage register 9 needs to store the same amount of addresses as the addresses stored in the address storage register group 1. In other words, the error address storage register 9
needs to be composed of the same number of registers as the number of registers in address storage register group 1. Therefore, as the number of addresses stored in the address storage register #1 increases, a problem arises in that the configuration of the error address storage register 9 becomes larger.

The present invention has been made in view of the above, and its purpose is to save and retain multiple error addresses when a bus cycle error occurs without significantly increasing the size of the configuration. The purpose of the present invention is to provide an information processing device that can perform the following tasks.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention provides an information processing device that reads ahead a memory operand stored in an external storage, a first storage means for storing and holding an address; a selection means for selecting an external storage read address output from the first storage means and data to be read from the external storage; and contents selected by the selection means. and a second storage means for storing and holding a plurality of data occupying the external storage, and storing and holding an address or G read from the second storage means and an address read from the first storage means; If an error occurs during a read operation of the external storage, the selection means selects the address output from the first storage means. If an error occurs during the write operation of the external memory, the third storage means is controlled to store and hold the address output from the first storage means, and the second and control means for controlling the third storage means to store and hold the address when the address is read from the storage means.

(Function) In the above configuration, the present invention is normally provided in the read operation of the external memory, and when an error occurs during the read operation of the external memory, the address where the external memory is accessed is set as the error address. A single batch of data to be input/output is stored in a storage means for storing and holding, and then each error address is transferred to a dedicated storage means for storing each error address, and this error address is used as error information to perform interrupt processing. I have to.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the main part configuration of an information processing apparatus according to an embodiment of the present invention. This information processing apparatus is controlled by a microprogram system to pre-read operand data, and FIG. 1 shows a configuration for accessing external storage (not shown). Note that in FIG. 1, components with the same symbols as in FIG. 2 have the same functions, and their explanations will be omitted.

In FIG. 1, the information processing device has an address storage register BY (A) included in the information processing device shown in FIG.
P) 1, memory address register (MAR) 5, data storage register group 7, and error address storage register 9
In addition, it includes a selector 21 and control logic 23.

The selector 21 is a memory address register (MAR) 5.
This selects the address stored in the data bus 25 and the operand data read from an external storage (not shown) via the data bus 25. This selection operation is performed in accordance with a selection signal given from the Ill'aO chic 23. The selected address or operand data is given to the data storage register 7 and stored therein.

The control logic 23 includes a microinstruction control section (not shown).
In accordance with signals given from an external circuit (not shown) that outputs signals related to bus cycles, address storage register group 1, memory address register 5, data storage register group 7, and error address storage register 9
and controls the selector 21.

The control logic 23 converts the AP select signal into an address storage register according to the microinstruction control signal given from the microinstruction control unit. Give to ff 1.

This AP select signal is a signal that selects and specifies a register that stores a read address (read address) or an old address (write address) of external storage on the internal bus 11 from among address storage register group 1. be.

The control logic 23 also provides an address latch signal to the memory address register 5. This address latch signal transfers the address stored in address storage register group 1 to MA'R5, and also transfers the address stored in address storage register group 1 to address bus 27.
This is a signal given to external storage via the .

The control logic 23 provides a DP select signal to the data storage register group 7 in synchronization with a bus cycle end signal provided from an external circuit. Further, a selection signal is applied to the selector 21 so that the operand data read from external storage is selected. On the other hand, when the bus cycle error signal and the bus cycle end signal are supplied to the control logic 23, the control logic 23 supplies a selection signal to the selector 23 so that the error address held in the AMR 5 is selected.

Furthermore, when the error address is read from the data storage register group 7 to the internal bus 11, the control logic 23
An interrupt signal is output to the microinstruction control unit to request interrupt processing. At the same time, the control logic 23
An AR (error address latch) signal is applied to the EAR9 so that the error address read onto the internal bus is taken into the EAR9 and saved. This EAR signal is
When the external storage is in the 1-in state, this signal is used to cause the EA 119 to take in and save the address held in the MAR5.

Next, the operation of this embodiment will be explained.

First, a case will be described in which a bus cycle error occurs during a read operation of external storage.

The microinstruction control signal is sent from the microinstruction control unit to
When applied to the 6110 switch 23, the AP select signal is sent from the control logic 23 to the address storage register group 1.
given to. As a result, the read address on the internal bus 11 is captured and stored in the register specified by the A P t left signal.

Next, the address latch signal is il, lI control logic 23
When the read address is given to MAR5 from MAR5, the read address stored in address storage register group 1 is transferred to MAR5 and held there. Furthermore, this read address is M
It is output from AR5 and applied to external storage via address bus 27. This starts a read cycle for reading operand data from external storage.

When this read cycle is completed, the bus cycle end signal 5
is applied to the control logic 23, the selection signal 11 is applied to select the operand data read from external storage.
1111110 is given to the selector 21 from the switch 23. Further, a DP select signal specifying a register to store the read operand data is applied to the data storage register group 7 in synchronization with the bus cycle end signal. Thereby, the operand data read from the external storage is applied to the designated register of the data storage register group 7 via the data bus 25 and the selector 21 and is stored therein.

On the other hand, if a bus cycle error occurs during a read operation of external storage and a bus cycle error signal is given to the control logic 23 at the same time as the bus cycle end signal, the MAR
A selection signal is applied to selector 21 to select the address stored in 5, that is, the error address. Further, a DP select signal is applied from the control I [ ] chic 23 to the data storage register group 7 . This allows MA
The error address stored in R5 is selected by the selector 21 and given to and stored in the register designated by the DP select signal.

Next, when the contents stored in the data storage register group 7 are read out to the internal bus 11 by a microinstruction,
If the read content is an error address, an interrupt signal is output from the control logic 23 to the microinstruction control section to request interrupt processing.

Further, the EAR signal is applied from the control logic 23 to the error address storage register 9. As a result, the error 7 address read onto the internal bus 11 is taken into the error address storage register 9 and saved. The saved error address is read onto the internal bus 11 by an interrupt processing microprogram activated by an interrupt signal and is pushed onto the stack.

Next, a case will be described in which a bus cycle error occurs during an external memory write operation.

First, the write address given on the internal bus 11 is
Upon execution of the microinstruction, the data is fetched and stored in the register specified by the AP select signal in the address storage register group 1. Similarly, write data is applied to and stored in the register designated by the DP select signal of the data storage register group 7. At the same time, an address latch signal is applied to MAR5, and the write address is transferred from address storage register 8Y1 to MAR5 and held, and is also applied to external storage via address bus 27. As a result, a write cycle for occupying data in external storage is started.

During this write cycle, when a bus cycle error occurs and the bus cycle error signal is applied to the control logic 23 together with the bus cycle end signal, the EAR signal 6 is applied from the control logic 23 to the EAR 9. As a result, the write address, that is, the error address held in MAR5 is copied to EAR9. Furthermore, at the same time, an interrupt signal is output to the microinstruction serial component. After the interrupt signal is output, the error address stored in the EAR 9 is pushed onto the stack via the internal bus 11 in the same manner as in the read cycle.

In this way, when a bus cycle error occurs during a read operation of external storage, the error address for this bus cycle error is temporarily stored in the data storage register group 7 and then transferred to the error address storage register 9. I'm trying to store it. On the other hand, during the write operation of external storage, the error address is directly stored in the error address storage register 9.

With this, even if a plurality of error addresses occur due to pre-reading, it is only necessary to provide one dedicated register for storing the error addresses. therefore,
The error address storage register can be made smaller than the conventional one. Furthermore, the interrupt processing microprogram only needs to push an error address onto the stack for one error address storage register.

Therefore, the microprogram for interrupt processing can be simplified compared to the conventional system in which it corresponds to a plurality of error address storage registers.

[Effects of the Invention] As explained above, according to the present invention, an error address corresponding to an error that occurs during a read operation of an external memory is normally provided in one read operation of an external memory, and a plurality of data can be stored. After temporarily storing and retaining the error address in the storage means for holding it, the error address is transferred to the dedicated storage means for storing each error 7 address and interrupt processing is performed, so that the structure does not need to be enlarged. , it becomes possible to save and hold multiple error addresses.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an information processing device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional information processing device.
It is a diagram. 1... Address storage register 8T 5... Memory address register 7... Data storage register group 9... Error address storage register 23... Control logic

Claims (1)

[Scope of Claims] An information processing device that prefetches a memory operand stored in an external storage, comprising: a first storage unit that stores and holds an address for accessing the external storage; and an output from the first storage unit. a selection means for selecting a read address of the external storage to be read and data to be read from the external storage; a second storage means for storing and holding a plurality of contents selected by the selection means and data to be written to the external storage; , a third storage means that stores and holds an address read from the second storage means or an address read from the first storage means, and from which the stored address is read when executing an interrupt process; and a third storage means of the external storage. If an error occurs during a read operation, the selection means selects the first
control to select an address output from the storage means, and if an error occurs during a write operation of the external memory, the third storage means stores the address output from the first storage means. and control means for controlling the third storage means to store and hold the address when the address is read from the second storage means. Processing equipment.