JPH02176143A - Pulse producing device - Google Patents

Abstract

PURPOSE:To perform engine control by CPU in sufficient time in terms of a pulse producing device for automotive engine control by processing the interruption of fuel injection start and finish timings with macroservice. CONSTITUTION:A CPU 100 terminates its instruction execution process when a preset data processing request is given from an interruption request producing circuit 110, operates a conveyor register and a capture register in a peripheral headware 115 and a data memory 114 in accordance with informations from a configuration instructing means 112, and processes the interruption of fuel injection start and finish timings with macroservice. Since there is not vector interruption request, no CPU time is necessary for the evacuation or return of a program counter 106 and a program execution holding means 107 during the shift to a interruption processing program, in spite of increasing engine revolution. It is thus possible for a microcomputer to perform engine control in sufficient time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generator, and more particularly to a pulse generator for generating fuel injection pulses for controlling an automobile engine.

[Conventional technology]

Recently, many microcomputers have been used in automobile engines. The most important control in engine control is fuel injection control, and the microcomputer calculates the standard injection amount from the intake air amount and engine speed, and compares the current temperature and The optimum fuel injection amount is converted into injection time by multiplying it by a correction coefficient obtained from measured values such as the amount of oxygen contained in exhaust gas, and fuel injection is performed for each cylinder by activating the output boat for the desired injection time. I do.

Normally, a specific position in the rotation cycle for each cylinder, such as a signal indicating top dead center or intake start timing, is used as a reference signal, and using this as an interrupt signal, the microcomputer uses the reception 1 interrupt processing program to inject fuel from the reference point. Use hardware such as a timer to set the start time.

Then, the output port is set to active level by the interrupt processing program that is activated by the interrupt signal from the timer, and then the fuel injection end time is set using the timer again.Next, it is activated by the interrupt signal from the timer. The interrupt processing program executed makes the output boat inactive and ends fuel injection.

Figures 7(a) and (b) show the fuel injection pulse generation pattern (horizontal axis is time) for a four-cylinder engine.From the four output boats Po to P3 in Figure 0, each cylinder is A fuel injection pulse is output in a time period corresponding to . The rising edge of the pulse indicates the timing to start fuel injection, and the falling edge of the pulse indicates the timing to end fuel injection. There is a reference signal timing before the fuel injection start timing, which is shown in Fig. 7(a) and (b).
), and the high-level period of the pulse indicates the fuel injection time, that is, the fuel injection amount, and the longer the high-level period, the greater the fuel injection amount. The pulse generation pattern in fuel injection control takes various forms depending on the control method, but in this example, the most detailed control is possible by controlling each cylinder independently.

Figure 7(a) shows the pattern of fuel injection pulses when traveling at low and constant speeds, with no overlapping pulses for each cylinder, and Figure 7(b) shows the pattern of fuel injection pulses during rapid acceleration. This is a state in which pulses for each cylinder overlap in a pattern. The actual pulse pattern will be a random combination of these two examples depending on the situation at the time, making control of pulse generation from the output port more complicated.

Hereinafter, a conventional example of a pulse generator will be described with reference to FIGS. 8 and 9.

FIG. 8 is a system block diagram of the conventional example.
In this conventional example, a data bus 400 and an address bus 40
1, an arithmetic and logic unit (hereinafter referred to as ALU) 201, a temporary register 202, a general-purpose register 203 that acts as a high-speed storage means, and an address buffer 204 (expressed as AB in IJ)
, micro address generation unit (hereinafter referred to as μ address generation unit) 205.10 gram counter (hereinafter referred to as PC)
206 + means for maintaining the program execution state (hereinafter referred to as PsW) 207, microprogram ROM
(hereinafter referred to as μROM) 208 and timing system f3
Central processing unit (hereinafter referred to as CPU) including 11 parts 209
200, an interrupt request generation circuit (hereinafter referred to as INTC) 210 including an interrupt request flag 211, a program memory 212, a data memory 213, and one peripheral hardware 214. Note that in FIG. 8, abbreviations in parentheses are shown.

The INTC 210 accepts several interrupt signals from external hardware, selects one interrupt source with the priority assigned to each separate interrupt source, and sets the interrupt request flag 211 corresponding to that interrupt source. do9
When there are n interrupt requests, n interrupt request flags 211 are set, but in FIG. 8, only one interrupt request flag 211 is shown as an example. In addition.

Interrupt signals from external hardware, a priority order determining section, etc. are not shown.

Conventional interrupt processing is usually called vectored interrupt, and a vector table space is set in advance in the memory space, and this space stores the entry address of the interrupt processing program corresponding to each separate interrupt source. has been done. When a vectored interrupt occurs, a branch is made to the entry address corresponding to the interrupt source.

FIG. 9 is a block diagram of the peripheral hardware 214 in a conventional example. The peripheral hardware 214 corresponds to the data bus 400, and includes a free running timer 215 based on a clock, a compare register 216.2LL, and a clock-based free running timer 215.
219, 220. and 221, capture register 2
17, Boat register 223 and Bar 1 Hua 224
A boat output circuit 222 including
It is composed of P.

In this example, in the interrupt processing program using the reference signal, a value specifying the fuel injection start timing is set in the compare register 216, and the match signal of the compare register 216 gives the fuel injection start timing for all four cylinders, and the compare register 216 is set to a value specifying the fuel injection start timing. The match signals from registers 218-221 are tR-configured to provide fuel injection end timings corresponding to output ports PQ-P3, respectively.

Note that the match signals from each of the compare registers are output to the INTC 210 as interrupt request source signals, and in FIG. 9, the match signals are expressed as INT.

Hereinafter, it is assumed that all signals expressed in INT have the same meaning.

In the following, the compare register 216 is set to output port P in advance by an interrupt processing program using a reference signal.

Assuming that a value specifying the fuel injection timing corresponding to 2 is set, the operation will be explained from the point where the match signal from the compare register 216 is generated.

In FIG. 8, in normal instruction processing, the program address stored in the PC 206 is transferred to the address buffer 2.
04 and drives the address bus 401,
Seven instructions to be executed next are fetched from program memory 212. The fetched instructions are transferred to the μ address main unit 205 via the data bus 400. The μ address main generator 205 converts μRO from the transferred instruction code.
Generate an address for M20g. From then on, μROM 20
The instruction is processed by manipulating the general-purpose register 203, ALU 201, temporary register 202, etc. according to the instructions of the μ program for the instruction stored in g.

The INTC 210 constantly samples whether or not an interrupt request is generated from the peripheral hardware 214, independently of the processing in the CPU 200, and if a request is generated, selects one request and sends it to the request source. Set the corresponding interrupt request flag 211.

When a match signal is generated from the compare register 216,
The capture register 217 captures the value of the free running timer 215 at that time, and the match signal from the compare register 216 generates an interrupt request to the INTC 210, which accepts the interrupt request and issues an interrupt request. When the flag 211 is set, the interrupt request signal 403 is sent to the timing control unit 20.
9 is output.

The last command of the μ program is a command to detect whether or not an interrupt has occurred. When this command is issued, the timing control unit 209 sends a 1-interrupt request signal 403.
If the interrupt request signal 403 is active, the interrupt request clear signal 402 is set to INTC.
210 and clears the interrupt request flag 211.

Next, the PC 206 and PSII 207 are saved to the stack space pointed to by the stack pointer (a register set in the CPU 200, but not shown), and the vector set at a specific address in the data memory 213 is saved. The entry address of the interrupt processing program corresponding to the interrupt source stored in the table is read and set in the PC 206 via the data bus 400. The interrupt processing program starts execution from the program address newly set in the PC 206.

In the interrupt processing program, first, the boat register 22
By setting bit 0 of 3 to “1”, output port P
The output pulse from o is set to high level, and the output port P.

data corresponding to the fuel injection pulse width in the corresponding cylinder are added and the result is transferred to the compare register 218.

In the processing of the instruction that terminates the interrupt processing program, the PC value and PSII value saved in the stack space are restored to the PC 206 and PS 11207, respectively, so that processing from the next instruction at the time when the interrupt occurs is executed. resume.

Next, when a match signal from the compare register 218 indicating the fuel injection end timing is generated during normal instruction execution, the tNTc 210 accepts the interrupt request and the interrupt request signal 403 is sent to the timing controller 209.

When a command is issued from the μ program to detect whether or not an interrupt has occurred, the timing control unit 2
09 samples the presence or absence of 1 interrupt request signal 403 0
If the interrupt request signal 403 is active, the interrupt request clear signal 402 is output to the INTC 210 and the interrupt request flag 211 is cleared.

Next, the PC 206 and PS 11207 are saved to the stack space, the interrupt processing program branches to the entry address of the interrupt processing program corresponding to the interrupt source stored in the vector table set at a specific address in the data memory 213, and interrupt processing starts. The program begins running.

Since the interrupt processing program is a fuel injection termination process for the output port Po, by setting bit 0 of the 2-board register 223 to "0", the output pulse from the output port (Pa) is set to a low level, and the corresponding cylinder Terminate fuel injection for.

In the processing of the instruction that terminates the interrupt processing program, the PC value and psw value saved in the stack space are restored to the PC 206 and PSW 207, thereby allowing processing from the next instruction at the time the interrupt occurs. resume. Similar processing is also performed for the output boats P to P.We have explained one conventional example of a pulse generator for automobile engine control. The processing functions are as described above.

[Problem to be solved by the invention]

In the above-described conventional pulse generator, the microcomputer receives a reference signal for outputting a fuel injection pulse as an interrupt signal, and controls settings such as fuel injection time using an interrupt processing program. Therefore, as the engine speed increases and the number of times the reference signal is generated increases, many interrupt requests such as reference signal interrupt, fuel injection start interrupt, and fuel injection end interrupt occur, and the PC value and PSW value at that time increase. When saving the contents of the stack to the stack or returning to the main process from the interrupt processing program, the process of restoring the contents of the stack to the PC 206 and PSW 207 frequently occurs, and the CP used for saving and restoring is
U time becomes a huge amount of time.

On the other hand, in addition to fuel injection control, the C20 also performs various miscellaneous tasks such as ignition timing control and idle rotation control, and as the engine speed increases, the CPU time devoted to these main processes decreases. In some cases, processing that cannot be handled at all may occur.

Therefore, it has become extremely difficult to control the engine using a microcomputer in modern vehicle models equipped with high-speed rotation and multi-cylinder engines.

In addition, in modern engine control, highly accurate fuel injection control is required due to requirements such as exhaust gas regulations and fuel cost savings, and fuel injection start timing and fuel injection end timing can be controlled with minimal error. , and it is becoming necessary to separately spend $1111 for each cylinder. Conventional methods of controlling these requests using only software processing result in a time delay between the occurrence of an interrupt factor and the start of the interrupt processing program, and a delay due to the time it takes to write data to the output port. In order to perform highly accurate control, dedicated hardware is required that has a resolution several steps higher than a series of processing cycles and is based on signals within the control tolerance range. This includes a timer that counts up the number of clocks, a capture register that stores the timer value when a certain event occurs, and a predetermined value for the timer. Requires dedicated hardware such as a compare register to indicate when a match has been made. Here, the capture register is used to store the fuel injection start timing, and the compare register is used to store the fuel injection start timing.
Used to generate fuel injection start timing and end timing. As mentioned above, the output pulses from the output boat take various patterns, such as overlapping and non-overlapping, so it can be done without any software intervention using just two compare registers for fuel injection start timing and end timing. Control corresponding to four cylinders is not possible. Therefore, in order to perform control using only hardware, four sets of compare registers are required, which increases the amount of hardware and becomes an economic burden. Naturally, as the number of cylinders increases to 6 or 8, the number of compare registers also increases to 6 or 8, which is especially burdensome when applied to a configuration in which the CPU and nearby circuits are integrated on a single board, such as a single chip. increases.

In relation to the reference signal fuel injection start timing, the air R(
If the reference signal is selected so that the reference signal for n+1> comes later in time, only one capture register and one compare register that generates the fuel injection start timing can be configured, as shown in Fig. 9. Good, but the cylinder (n
) than the fuel injection end timing! J(n+1
), the fuel injection start timing may be earlier in time, so the compare register that gives the fuel injection end timing must be installed for the number of cylinders, which also results in an increase in the amount of hardware. becomes.

In other words, in order to respond to the recent high precision of automobile engine control, conventional pulse generation circuits must have a resolution several steps higher than a series of I control processing cycles, and must generate signals within the allowable error range in terms of ll1w accuracy. It is necessary to add dedicated hardware based on the above to perform direct control by the hardware, which has the disadvantage that the amount of hardware including the above-mentioned dedicated hardware increases significantly.

[Means to solve the problem]

The pulse generating circuit of the present invention is a means for generating a request for asynchronous interrupt processing to the CPU and also generating a request for predetermined data processing in a pulse generating device for controlling an automobile engine using a CPU. , a mode specifying means for identifying the interrupt processing request and the predetermined data processing request; and processing mode information specifying the processing mode of the predetermined data processing together with necessary data. a data memory that also stores data, a predetermined 7-lead running timer, a compare register,
Peripheral hardware including a capture register that captures the value of the free running timer at a predetermined timing, a plurality of output ports for generating injection pulses for engine control, and a PC that holds execution addresses of instructions; The T
A request for the predetermined data processing is generated from the NTC,
If the format instruction means detects that the predetermined data processing is instructed, the instruction execution process is interrupted, and the compare register, the capture register, and the data memory are stored in accordance with the processing format information. and the PCU which, when operated, controls fuel injection pulses for controlling the automobile engine output from the plurality of output boats.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a system block diagram of a first embodiment of the present invention, and FIG. 2 is a professional diagram of peripheral hardware in the first embodiment.

As shown in FIG. 1, in the first embodiment, an AL
U101, temporary register 102, general-purpose register 103, address buffer 104, μ address generation unit 105, PC106, PS11107, μROM
CPLI including 108 and timing control unit 109
100, an interrupt request flag 111, and a format specification flag 112 [NTC 110, program memory 1]
13, data memory 114, and peripheral hardware 11
5.

Further, as shown in FIG. 2, peripheral hardware 11
5 is a free running timer 116, a compare register (denoted as ecOMPl in the diagram) 117, a compare register (described as C014P2 in the diagram) 119, a capture register (described as CAP in the diagram) 118, and a bit selection register. (SR) 120, bit selection register (RR) 121, and four AND games each)
4#i R corresponding to I11 control circuits 122 and 123 including 124 and four output ports Po5P, respectively.
A boat output circuit 125 including an S flip 70 tube 126 and a buffer 127 is provided.

The INTC 110 accepts several interrupt signals from external hardware, determines the priority assigned to each separate request source, selects one interrupt source with the highest priority, and processes that interrupt source. The corresponding interrupt request flag 111 is set. When there are n interrupt requests, n 111 included request flags 111 and mode specification flags 112 are each set, but in order to simplify the explanation, only one set is shown in the figure. There is.

Furthermore, an interrupt signal from external hardware, a priority order determining section, and the like are not particularly shown because they are not directly related to the gist of the present invention.

Interrupt request from INTC110 is sent to CPU 100
can be processed in two ways. One is the conventional vector interrupt processing, and the other is a processing form that is a feature of the present invention. When an interrupt request occurs, data memory 114 is processed without referring to the vector file. This is a processing mode in which predetermined data processing is executed based on processing mode information preset to a specific address in . Hereinafter, this predetermined data processing will be referred to as a macro service. Regarding the classification of the above two processing types, designation of vector interrupt or macro service is performed using the type designation flag 112. When "0" is designated in the designation flag 112, it is designated as a vector interrupt, and when "1" is designated, it is designated as a macro service.

Next, processing type information that specifies the processing type of the macro service of the present invention will be explained. FIG. 3 is a diagram showing an example of the % physical information structure of a macro service, and FIG. 4 is a diagram showing a macro service processing flowchart in the first embodiment.

The processing mode information is located at a specific address in the data memory 114, and the processing mode information in this embodiment includes a 2-byte header section containing a macro service mode and a channel pointer (indicated as PTR in FIG. 3). , consisting of a 13-byte macro service channel pointed to by the channel pointer. The macro service channel of this embodiment is configured assuming 4-air fuel injection control, and the initial counter (denoted as [old T in Fig. 3)]
, reset data specifying the fuel injection pulse width, - a word buffer (Pa~) that temporarily stores the fuel injection pulse width;
P3), a write counter indicating the write position for the word buffer (described as !lRCNT in Figure 3)
, and a read counter (indicated as RD CNT in FIG. 3) that indicates the read position from the word buffer.

In the compare register 117, data indicating a displacement from a reference signal to a fuel injection start timing in fuel injection control is stored by the CPjJ 100. The data setting timing is set by the interrupt processing program at the time when the reference signal generates an interrupt. As described in the conventional example, in this embodiment, only one compare register 117 is used to select a reference signal for giving fuel injection start timing to a plurality of cylinders.

The macro service of this embodiment is the compare register 117
and the match signal 30g from the covair register 119. Before the macro service is started, the CPU 100 initializes the macro service channel and hardware.If the cylinder is 4 cylinders, the CPU 100 sets 4 to 1N[T, WRCNT, and RD CNT of the macro service channel. In addition, the bit selection register (SR) 120 and the bit selection register (RR> 121) are set to specify that the output port that should output the fuel injection pulse first is Po. . only the bit corresponding to '1
", and other values are set to 0".

The macro service will be explained below in response to the fuel injection pulse patterns shown in 7th tM (a) and (b).

In the case of the fuel injection pulse pattern shown in FIG. 7<a>, when the match signal 307 from the compare register 117 is first generated, the RS flip-flop corresponding to the output boat PO is selected from the initial value of the bit selection register SR120. Only port 126 is set, and output port P. The output level from the cylinder becomes high level, and fuel injection to cylinder 0 is started. At the same time, the value of free-running timer 11.6 is stored in capture register 118 by coincidence signal 307. The match signal 307 also generates one interrupt request to fNTcllo. rNTc
110 outputs a match signal 307 via data bus 300.
When receiving this source, the interrupt request flag 111 corresponding to this source is set and the interrupt request signal 303 is activated. The timing control unit 109 samples the interrupt request signal 303 at the end of instruction processing, and since the interrupt request signal 303 is active, it samples the format designation signal 305. When detecting that the format specification signal 305 is “1” indicating macro service, the PC 10
6 and PSll 107, μROM
Generate a 10g macro service processing entry address and start the macro service. Thereafter, macro service processing is executed according to the μ program command of the macro service.

The processing flow according to the μ program command will be explained below using the flowchart shown in FIG.

First, the header of the macro service using the match signal 307 as an interrupt source is read from a specific address in the data memory 114. In this case, the macro service mode is set to ML (mode name) in advance. When the macro service mode is Ml, IJRCNT, RD
CNT, +7) Make a comparison.

Since the initial value of both WRCNT and RD CNT- mentioned above is 4, the contents of the capture register 11g and the reset data in the macro service channel are transferred to the ALU.
101 and stores the result in the compare register 119. Reset data is CPU 10
0 and the macro service is
The reset data, which is the latest fuel injection time, will be used.

Next, WRCNT is decremented by 1 to 3.
Since WRCNT is not O, the bit selection register (SR
> Execute left shift processing of 120 and set only the bit corresponding to the output port PI to 1. In this case, shift-out does not occur, so the timing control unit 109 outputs the interrupt request clear signal 302 to the INTe 110, resets the interrupt request flag 111, and ends the macro service processing. When the macro service processing is completed, the timing control unit 109
Normal instruction processing resumes from the values of C106 and I'SW 107.

In the case of the pulse pattern shown in FIG. 7(a), since there is no overlapping of pulses, a match signal 308 is generated from the compare register 119 next. Bit selection register (R
R) 121 is the output port P because only the bit corresponding to the output port Po is 1 and the bits corresponding to the other output ports are 0. RS flip-flop 126
only is reset, and fuel injection to cylinder 0 ends. The above match signal 308 generates an interrupt request to INTC 110.

When the INTC 110 accepts the interrupt request of this match signal 308, it sets the interrupt request flag 1 corresponding to this source.
11 and activates the interrupt request signal 303. The timing control unit 109 samples the interrupt request signal 303 at the end of instruction processing, but since the interrupt request signal 303 is active, the format designation signal 3
Sample 05. As a result, when it is detected that the format designation signal 305 is "1" indicating macro service,
μRO while holding PC106 and PSW 107
A macro service processing entry address of M108 is generated and macro service processing is started.

In macro service processing, first, the match signal 30
The header of the macro service whose interrupt source is 8 is read from a specific address in the data memory 114. This specific address is assigned a different address from the address corresponding to the match signal 307 described above. Further, the macro service mode is set to M2 (mode name) in advance, and the channel pointer points to the macro service channel corresponding to the match signal 307.

When macro service mode is M2, RD CNT.

Decrement by 1 to make it 3. RD CNT,
is not 0, so proceed to the next process, and RD CNT is 3 as described above, and %IRCNT is also 3 in the macro service processing on the fuel injection start timing side.
RD CNT, = WRCNT, and the process proceeds to the next step.

In the left shift process of the bit selection register (RR) 121, only the bit for the output port P□ becomes 1, and the other bits become 0. Therefore, since shift-out does not occur, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, resets the 1-interrupt request flag 111, and ends the macro service processing. When the macro service processing is completed, the timing control unit 109 updates the PC 106 and PSW that were held.
The process of 0 or more, which restarts normal instruction processing from the value of 107, is repeated in exactly the same way from output ports P to P3.

Similarly, in the macro service activated by the fuel injection start timing for the output port P3, since the macro service mode is Ml, the ridge CNT and RD C
In this case, since both WRCNT and RD CNT are 1, the contents of the capture register 11g and the reset data in the macro service channel are added using the ALU 101, The result is stored in the compare register 119.

Next, WRCNT is decremented by 1 and set to O.
Since WRCNT is 0, the value 4 of INIT is set to WRC
NT, reset to 9 then bit selection register SR1
When the left shift processing of 20 is executed, a shift out from bit selection register (SR) 120 occurs, so
The timing control unit 109 inputs the form change signal 304
It is output to the TC 110 and the format designation flag 112 is reset.

Since the INTC 110 has the interrupt request flag 111 in the set state and the format specification flag 112 in the reset state, in this case, the INTC 110 sends a normal vector interrupt request to CPυ
The 0 interrupt processing program, which is generated for 100 and executes the vector interrupt processing described above, is started when the 4 cylinders have completed one cycle, and the bit selection register (SR)
120 is reset to the initial state to prepare for fuel injection pulse output from the output port Po.

Next, in the macro service activated by the fuel injection end timing for output port P, since the macro service mode is M2, 1 of RD CNT,
Decrement it to O.

Since RD CNT becomes O, IN to RD CNT
Set the IT value to 4. RD CNT is 4, II
RCNT is also set to 4 in the macro service processing on the fuel injection start timing side. WRCNT = RD C
NT, and the process proceeds to the next step.

Since a shift out occurs due to the left shift processing of the bit selection register (RR) 121, the timing control unit 1
09, the form change signal 304 is INTCIICIG:
The format designation flag 112 is reset.

In the tNTc 110, the interrupt request flag 111 is in the set state and the format specification flag 112 is in the reset state, so in this case, a normal vector interrupt processing request is generated to cpu too, and the above-mentioned vector interrupt Execute processing. The interrupt processing program that is started at the timing of the end of fuel injection is also started when the four cylinders have completed one cycle, and the bit selection register (RR)
121 to the initial state and output port P. Prepare for fuel injection pulse output from.

Next, in the case of the fuel injection pulse pattern shown in FIG. 7(b), a match signal 307 is generated from the compare register 117 first, and only the RS flip-flop 70 knob 126 corresponding to the output port PQ is set. , output port P,
The output pulse from the cylinder becomes high level, and fuel injection to the cylinder O is started. Also, the match signal 307 generates an interrupt request to INTC1i0 to start the macro service. The processing procedure up to this point is exactly the same as in the case of FIG. 7(a) described above.

In this case as well, since the macro service mode is Ml, IIRCNT and RD CNT are compared. Since both IIRCNT and RD CNT have initial values of 4, the contents of the capture register 118 and the macro service channel are compared. The reset data inside, ALUlo
l is used to add the result, and the result is sent to the compare register 11.
Store in 9.

Next, WRCNT is decremented by 1 to 3.

+11RCNT is not 0, so the bit selection register (
SR) 120 left shift processing and output port P1
Set only the bit corresponding to . In this case, since no shift-out occurs, the timing control unit 10
9 outputs an interrupt request clear signal 302 to INTCllo, resets the interrupt request flag 111, and ends the macro service. When the macro service ends, the timing control unit 109
6 and the value of PSll 107, normal instruction processing is resumed and executed.

In the case of the seventh [M(b) pulse pattern, there is an overlap of pulses, and before the match signal 308 from the compare register 119 is generated, the match signal 307 from the compare register 117 is generated again. At this time, only the RS flip 70 knob 126 corresponding to the output port P1 is set, the output pulse from the output port P1 becomes high level, fuel injection to the air @1 is started, and the cylinder 0
Fuel injection will be performed for both the FJ1 and FJ1.

Match signal 307 generates an interrupt request to INTC 110 and starts macro service. In this case as well, since the macro service mode is Ml, WRCN
Unlike the previous case, where IIIRCNT is 3 and RD CNT is 4, the contents of the capture register 118 and the reset data in the macro service channel are compared with ALUolol. and the result is [PTR-gastric RCNT,
x2-4], that is, the address expressed by the formula [PTR-101, in this case stored in the word buffer (for Pt).

Next, IIRCNT is decremented by 1 to 2.

Since 11RCNT is not 0, left shift processing of the bit selection register (SR) 120 is performed and the output port P
Only the bit corresponding to 2 is set to 1. In this case, since no shift out occurs, the timing control section 1
09 sends the interrupt request clear signal 302 to [NTCI
10, resets the interrupt request flag 111, and ends the macro service.

When the match signal 307 from the compare register 117 is generated again, this time the RS corresponding to the output port P2 is
Only the flip 70 knob 126 is set, the output pulse from the output port P2 becomes high level, and fuel injection to the cylinder 2 is started.

The match signal 307 generates an interrupt request to the INTC 110 and starts the macro service. Also in this case,
Since the macro service mode is Ml, IlRCNT
, and RD CNT, IIIRCNT
, is 2, and RD CNT is 4, so the contents of the capture register 118 and the reset data in the macro service channel are added using the ALU 101, and the result is [PTR-WRCNT, x2-4 ] That is, the address expressed by the formula [PTR-8], in this case stored in the word buffer (for P2).

Next, IIRCNT is decremented by 1 to 1.

Since WRCNT is not 0, the bit selection register (
SR) 120 left shift processing and output port P3
Set only the bit corresponding to . Since shift-out does not occur in this case as well, the timing system error 109 outputs the interrupt request clear signal 302 to [NTCllo, resets the interrupt request flag 111, and ends the macro service processing.

When the match signal 307 from the compare register 117 is generated again, at this time only the RS flip 70 1126 of the output port P3 is set, the output pulse from the output port P becomes high level, and the fuel for cylinder 3 is set. Injection begins.

The match signal 307 generates an interrupt request to the INTC 110 and starts the macro service. Also in this case,
Because the macro service mode is Ml.

Compare WRCNT and RD CNT, W
Since RCNT is 1 and RD CNT is 4, the contents of the capture register 118 and the reset data in the macro service channel are added using the ALU 101, and the result is [PTR-WRCNT,x2- 4
] That is, (address expressed by the formula PTR-61, in this case stored in the word buffer (for P3).

Next, IIRCNT is decremented by 1 and set to 0.

When WRCNT becomes 0, the value of tNIT is changed to WRCN.
Reset to T. and bit selection register (SR)
120 left shift processing is executed. Since shift-out occurs at this time, the timing control unit 109 outputs the format change signal 304 to the INTC 110 and resets the format designation flag 112.

The INTC 110 has the interrupt request flag 111 set to:?
In this case, the normal vector interrupt request is
In the 0 interrupt processing program that occurs to the PU 100 and thereafter executes the vectored interrupt processing described above, the bit selection register (SR) 120 is reset to the initial state,
Prepare for fuel injection pulse output from output boat P0.

Next, the output boat P. Match signal 308 from compare register 119 giving the fuel injection end timing for
occurs, the bit selection register (RR) 121
Only the bit corresponding to the output port P is 1 and the others are O, so the output port P. Only the RS flip 70 knob 126 corresponding to is reset, and fuel injection to cylinder O is terminated. This signal 308 is the INTC
110, and the macro service is started. Since the macro service mode in this case is M2, RD_CNT is decremented by 1 to 3. Since RD CNT is not 0, proceed to the next process,
Since RD CNT is 3 and WRCNT is initially set to 4 by the macro service processing on the fuel injection start timing side, WRCNT and RD CNT do not match, and [PTR-RD CNT, x2- 4] That is, the address expressed by the formula [PTR-101] and data indicating the fuel injection pulse width stored in the word buffer (for Ps) are transferred to the compare register 119.

Due to the left shift processing in the bit selection register (RR) 121, only the bit for the output port P1 becomes 1, and the other bits become O. In this case, since shift-out does not occur, the timing control unit 109 outputs the interrupt request clear signal 302 to INTCllo, resets the interrupt request flag 111, and ends the macro service.

Next, a coincidence signal 308 from the compare register 119 giving the fuel injection end timing for the output capo Pi
occurs, the bit selection register (RR) 121
Since only the bit corresponding to the output boat PL is 1° and the others are 0, only the RS flip 70 knob 126 corresponding to the output boat P is reset, and fuel injection to the cylinder 1 ends. This signal 308 is the INTC
An interrupt request is generated to 110, and macro service processing is started.

Since the macro service mode in this case is also M2, R
Decrement D CNT by 1 to make it 2. R.D.
Since CNT is not 0, proceed to the next process and RDCNT
, is 2, and WRCNT is initially set to 4 in the macro service processing on the fuel injection start timing side, so WRCNT and RD CNT do not match, and [PTR-RD CNT, x2-4] That is, [
The address expressed by the formula PTR-81 and data indicating the fuel injection pulse width stored in the word buffer (for P2) are transferred to the compare register 119.

Due to the left shift processing in the bit selection register (RR) 12L, only the bit for the output port P2 becomes 1, and the other bits become 0. In this case, shift-out does not occur, so the timing control unit 109 outputs the interrupt request clear signal 302 to r_NTCllo, resets the interrupt request flag 111, and ends the macro service processing.

Next, a coincidence signal 308 from the compare register 119 giving the fuel injection end timing for the output boat P2
occurs, the bit selection register (RR) 121
Since only the bit corresponding to the output boat P2 is 1 and the others are 0, only the RS flip 70vp 126 of the output boat P2 is reset, and fuel injection to the cylinder 2 ends. 9 = match signal 308 is 1NTc 110
An interrupt request is generated to start macro service processing.

Since the macro service mode in this case is also M2, R
Decrement D CNT by 1 to make it 1. R
If D CNT is not 0, proceed to the next process and RD C
NT is 1 and IIRCNT is initially set to 4 by the macro service processing on the fuel injection start timing side, so WRCNT and RD CNT do not match.
[PTR-RD CNT,x2-4] i.e. (PT
R-6] address, word buffer (
The data indicating the fuel injection pulse width stored in the register (for P3) is transferred to the compare register 119.

Due to the left shift processing in the bit selection register (RR) 121, only the bit for the output port P becomes 1, and the other bits become 0. In this case, shift-out does not occur, so the timing control unit 109 outputs the interrupt request clear signal 302 to INTCllo, resets the interrupt request flag 111, and ends the macro service processing.

Next, a coincidence signal 30g from the compare register 119 giving the fuel injection end timing for the output boat P.
occurs, the bit selection register (RR) 121
Since only the bit corresponding to the output boat P3 is 1 and the others are O, only the RS flip 70 knob 126 of the output boat P3 is reset, and fuel injection to the cylinder 3 ends. This match signal 308 generates an interrupt request to the INTc 110 and macro service processing is initiated.

Since the macro service mode in this case is also M2, R
D CNT is decremented by 1 and becomes O. R
Since D CNT becomes 0, the value of IN[T is reset to 4. As a result, RD CNT, =IIRCNTt
= 4, no data is transmitted to the compare register 119, and the bit selection register (RR) 121
Shifts to left shift processing. In this case, since a shift out from the bit selection register (RR) 121 occurs, the timing control unit 109 controls the format change signal 304.
is output to the INTC 110, and the format specification flag 11 is
Reset 2. In the INTC 110, the interrupt request flag 111 is set, and the mode specification flag 112 is set.
Since it is in a reset state, in this case, a normal vector interrupt request is generated to CPυ100, and thereafter, the vector interrupt processing described above is executed.

In the interrupt processing program started at the fuel injection end timing, the bit selection register (RR) 121 is reset to the initial state to prepare for the fuel injection pulse output from the output boat P.

In this embodiment, a case is shown in which the fuel injection start timing for other cylinders does not occur before the fuel injection end timing of the output boat P3, but for example, before the fuel injection end timing of the output boat P3, the output boat P,
Assuming that the fuel injection start timing has occurred, in the macro service processing on the fuel injection start timing side, the result of adding the capture register 118 and the reset data is
[PTR-WRCNT,x2-4] i.e. [PTR
-12] address, word buffer (
11RCNT (for Pa), and then becomes 11RCNT, = 3, so in the macro service process that is started at the end timing of fuel injection of output capo (P3), IIRCN
T,=3 and RD CNT,=4, resulting in a mismatch. In this case, the address expressed by the formula [PTR-12], that is, the data stored in the word buffer (for Po), is transferred to the compare register 119. Also, the fuel injection end timing for the output boat P3 can be obtained logically and without contradiction.

Although the case of the pulse patterns shown in FIGS. 7(a) and 7(b) has been described above, the present macro service processing is applicable to any combination of these two patterns.

In addition, in this embodiment, the bit selection register (SR
) 120 and the bit selection register (RR>121), if a shift out occurs as a result of shift processing, a vector interrupt is generated and initialization is performed using the interrupt processing program. This is set to provide the timing of correction when some kind of correction processing is required depending on the state.In systems that do not require such correction processing, the bit selection register (SR) 120 or bit Selection register (RR
) 121, performs rotation processing and bit 3
If the macro service processing is changed so that the shift door current from the start is transferred to bit 0, complete fuel injection control will be possible with just the macro service processing without the occurrence of vector interrupt processing.

Next, the second embodiment of the present invention will be explained. Since the system block diagram of this embodiment and the structure of the macro service processing form information are the same as those of the first embodiment, the explanation will be as follows. Omitted. FIG. 5 is a block diagram of peripheral hardware in the second embodiment.

As shown in FIG. 5, the eleven peripheral hardware of this embodiment include a free running timer 128 and a compare register (C014P in the figure) corresponding to the data bus 300.
12 compare registers (denoted as I) and compare registers (denoted as C in the figure).
(written as OMP 2) 131, and a capture register (written as CAP in the diagram)! 30, and a delay circuit 132. i
33, bit selection register (SR) 134, bit selection register (RR) 135, and four ANDs each.
Control circuits 136 and 137 including gates 138 and four RS flips 7 corresponding to the four output ports Po to P3
A boat output port 139 including a zero tube 140 and four buffers 141 is provided.

In FIG. 5, match signals 310 and 311 are output from compare registers 129 and 131, respectively. The bit selection register (SR) 134 and the bit selection register (RR) 135 have a shift register configuration, and are controlled by signals from delay circuits 132 and 133.
Shift left by 1 bit. In the first embodiment, the bit selection register (SR
) 120 or bit selection register (RR) 121, but in this embodiment, the above-mentioned match signal 310 or 311 is transferred to the delay circuit 132 or 133.
The bit selection register (SR) 134 or the bit selection register (R
R) 135 shift processing is being executed.

Next, the macro service processing flow in this embodiment is shown in FIG. 6. The shift processing in the bit selection register (SR) 134 or the bit selection register (RR) 135 is performed by the delay effect by the delay circuit 132 or the delay circuit 133. As much as it was possible to execute it hardware-wise via
In contrast to the first embodiment, the shift processing portion executed by the μ program command of the macro service is deleted, and the processing speed of the macro service is improved. The other operations are exactly the same as those in the first embodiment, so detailed explanation will be omitted.

〔Effect of the invention〕

As described above in detail, the present invention processes interrupts such as fuel injection control timing interrupts and fuel injection end timing interrupts using macro services, and does not generate vector interrupt requests. PC and psw when transitioning to 1 interrupt processing program
The CPU time is not occupied in the process of saving the contents of the stack to the stack or returning the contents of the stack to the PC or PSI when returning from the interrupt processing program to the main process.

Therefore, it is possible to allocate sufficient CPU time to various miscellaneous tasks such as fuel injection control, ignition timing control, and idle rotation control in engine control, and the microcomputer can control the engine with sufficient margin even when the multi-cylinder engine rotates at high speed. It has the effect of being able to do the following.

In addition, in response to the need for highly accurate fuel injection control due to recent exhaust gas regulations and demands for reductions in fuel costs, we have added a compare register that provides fuel injection start timing and fuel injection end timing. By directly controlling the output boat and generating fuel injection pulses based on the coincidence signal from The engine can be controlled with minimal errors without time delays, and each cylinder can be controlled independently, making it possible to adjust the fuel injection amount with high precision. It also has the effect of becoming.

In addition, as shown in the conventional example, it is necessary to take various fuel injection patterns, including cases where the fuel injection pulses overlap and do not overlap, so the fuel injection start timing can be determined without software intervention. It is not possible to perform control corresponding to multiple cylinders with only two compare registers for start and end timing. In order to perform control corresponding to multiple cylinders, multiple sets of compare registers are required. Regarding the issue of an increase in the amount of hardware and an increase in economic burden, by applying macro service processing in which the same macro service channel according to the present invention corresponds at the fuel injection start timing and fuel injection end timing, it is possible to solve the problem. , IJII's compare register and capture register alone make it possible to control fuel injection for multiple cylinders without increasing the amount of hardware. This means that the number of cylinders is 6,
Even if the number is increased to 8, the same response can be achieved by simply increasing the number of word buffers in the macro service channel.
It is possible to construct an economically very advantageous engine control system, and it has the effect that it can be fully applied to a single chip in which a CPU and peripheral circuits are integrated on a single board.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of the first and second embodiments of the present invention, FIG. 2 is a block diagram of peripheral hardware in the first embodiment, and FIG. 3 is a macro service processing 4 is a diagram showing a macro service processing flowchart in the first embodiment, FIG. 5 is a block diagram of peripheral hardware in the second embodiment, and FIG. 6 is a diagram showing an example of configuration information configuration. , a diagram showing a macro service processing flowchart in the second embodiment, FIG.
) and (b) are diagrams showing the output turn of the fuel injection pulse from the output boat, FIG. 8 is a system block diagram of a conventional pulse generation circuit, and FIG. 9 is a diagram of peripheral hardware in the conventional example. It is a block diagram. In the figure, 100, 200...CPU,
101.201...ALU, 102,
202...Temporary register, 103゜20
3...-General purpose register, 104.204...
-・Address buffer, 105, 205...μ
Address generation unit, 106゜206-・----PC11
07,207----PSII, LO8,208
-...uROt4-109.209-== 9 Imink 1111m section, 110°210...-INTC
llll, 211... Interrupt request flag, 11
2...Form specification flag, 113.212...
...Program memory, L12.213...
Data memory, 115.214...-Peripheral hardware, 116,128.215...Free running timer, 117,119. L29.131,2
16.218°219.220,221--Compare register, 11L130°217--Capture register, 120,134. ...-Bit selection register (SR), 121.135...
Bit selection register (RR), 122, 123, 13
6,137...--control circuit, 124.138...
--AND gate, 125, 139, 222...
-・Boat output circuit, 126, 140...RS
Flip-flop, L27JIH, 224...-
Buffer, 132.133...delay circuit,
223・−・−・・Boat register.

Claims (1)

[Claims] A pulse generator for controlling an automobile engine using a central processing unit, which generates a request for asynchronous interrupt processing to the central processing unit and also generates a request for predetermined data processing. an interrupt request generation circuit including means for specifying a form for identifying the interrupt processing request and the predetermined data processing request; and specifying the processing form of the predetermined data processing along with required data a data memory that also stores processing mode information, a predetermined free running timer, a compare register, a capture register that captures the value of the free running timer at a predetermined timing, and an injection pulse generation for engine control. peripheral hardware including: a plurality of output ports for the computer, a program counter for holding execution addresses of instructions, means for holding the execution state of the program, high-speed storage means, and a microprogram ROM; When a request for the predetermined data processing is generated from the interrupt request generation circuit and the format instruction means detects that the predetermined data processing is instructed, the instruction execution process is interrupted and the processing format is changed. The central processing unit controls fuel injection pulses for automobile engine control output from the plurality of output ports by operating the compare register, the capture register, and the data memory according to information. A pulse generator featuring: