JPH0217677U

JPH0217677U -

Info

Publication number: JPH0217677U
Application number: JP9571288U
Authority: JP
Priority date: 1988-07-21
Filing date: 1988-07-21
Publication date: 1990-02-05

Description

[Brief explanation of drawings]

第１図乃至第６図はこの考案に係るレベル表示
装置の実施例を示し、第１図は実施例１のブロツ
ク図、第２図は実施例２のブロツク図、第３図は
実施例３のブロツク図、第４図は実施例４のブロ
ツク図、第５図は実施例５のブロツク図、第６図
は実施例６のブロツク図である。第７図は従来例
を示したブロツク図である。主な番号の説明、２：レベル検出回路、３：第
１のピークホールド回路、４：コントローラ、５
，２５：リセツトスイツチ、６：ピーク表示ＯＮ
／ＯＦＦの表示スイツチ、７：第２のピークホー
ルド回路、８，１０，２１，２３：ＡＮＤ回路、
１１：ＯＲ回路、１２：レベルメータドライブ回
路、１３：表示ドライブ回路、１４：レベル表示
器、２０：ピークホールド回路、２１：タイマ回
路、２２：タイマスイツチ。 1 to 6 show examples of the level display device according to this invention, FIG. 1 is a block diagram of the first embodiment, FIG. 2 is a block diagram of the second embodiment, and FIG. 3 is a block diagram of the third embodiment. 4 is a block diagram of the fourth embodiment, FIG. 5 is a block diagram of the fifth embodiment, and FIG. 6 is a block diagram of the sixth embodiment. FIG. 7 is a block diagram showing a conventional example. Explanation of main numbers, 2: Level detection circuit, 3: First peak hold circuit, 4: Controller, 5
, 25: Reset switch, 6: Peak display ON
/OFF display switch, 7: second peak hold circuit, 8, 10, 21, 23: AND circuit,
11: OR circuit, 12: Level meter drive circuit, 13: Display drive circuit, 14: Level display, 20: Peak hold circuit, 21: Timer circuit, 22: Timer switch.

Claims

[Claims for Utility Model Registration] 1. A level detection circuit, a first peak hold circuit that holds a short-time signal peak value, and the logic of the output signal of the level detection circuit and the output signal of the first peak hold circuit. In a level display device composed of a logical sum (OR) circuit that calculates the sum (OR), a level meter drive circuit for displaying on the level display, and a level display, A second peak hold circuit for holding the signal peak value of the second peak hold circuit, a reset switch for arbitrarily resetting the second peak hold circuit, and a display switch for turning on/off the output signal of the second peak hold circuit are provided. A level display device characterized in that it is configured to display on the level display device. 2 The reset switch that arbitrarily resets the second peak hold circuit and the display switch that turns ON/OFF the output signal of the second peak hold circuit are used, and when the output signal turns OFF, the second peak hold circuit
2. The level display device according to claim 1, wherein said level display device is configured to reset said peak hold circuit. 3 Turn on the output signal of the second peak hold circuit
2. The level display device according to claim 1, wherein the display switch that turns on/off also turns on/off the output signal of the first peak hold circuit. 4 The reset switch that arbitrarily resets the second peak hold circuit and the display switch that turns ON/OFF the output signal of the second peak hold circuit are used, and when the output signal turns OFF, the second peak hold circuit
4. The level display device according to claim 3, wherein said level display device is configured to reset said peak hold circuit. 5. The device according to claim 3, characterized in that, when the output signal of the second peak hold circuit is turned ON by a display switch, the peak character is displayed on a level display equipped with display means for displaying the peak character. Level display device according to 4. 6. A level detection circuit, a peak hold circuit for holding a signal peak value, a logical sum (OR) circuit that takes the logical sum (OR) of the output signal of the level detection circuit and the output signal of the peak hold circuit, and a level display. In a level display device consisting of a level meter drive circuit and a level display device, a timer circuit is provided to arbitrarily reset this peak hold circuit, and a reset signal by this timer circuit is turned ON/OFF. A level display device characterized by being equipped with a timer switch. 7. The level display device according to claim 6, further comprising a reset switch for arbitrarily resetting the peak hold circuit when the timer switch is OFF. 8. The level display device according to claim 6 or 7, characterized in that, when the reset signal is turned off by a timer switch, the peak character is displayed on a level indicator equipped with display means for displaying the peak character.