JPH0217746A - Modem reception circuit - Google Patents

Abstract

PURPOSE:To enable a means to function even in a viterbi decoder without using a hard decision point by feeding back data based on a recent symbol from the data in a trace memory obtained in decoding to jitter correction in a carrier automatic phase control part(CAPC). CONSTITUTION:To a branchmetric calculation means 121 included in the viterbi decoder 119, a reception code output signal 113 obtained by performing the jitter correction of a reception demodulating signal 111 by a carrier automatic phase control means 115 is supplied, and branchmetric is calculated based on the output signal 113, and the data of minimum passmetric is stored in a pass memory 123. A pass trace control means 125 performs pass trace based on the data stored in the memory 123, and stores a result in the trace memory 127 corresponding to a symbol. And the control means 115 performs the jitter correction by the data based on the recent symbol out of the data stored in the memory 127.

Description

[Detailed Description of the Invention] [Summary] To enable CAPC to perform its original function in a modem receiving circuit even when a received code is decoded by a Viterbi decoder that does not use hard decision points. For the purpose of A Viterbi decoder includes: a branch metric calculation means for calculating a branch metric based on a received code output signal; a path memory in which minimum path metric data based on the branch metric is stored; It has a path tracing control means that performs path tracing based on data stored in the memory, and a trace memory in which path tracing results are sequentially stored according to symbols. It is configured to be fed back for jitter correction in the carrier wave automatic phase control means.

[Industrial application field]

The present invention relates to a modem receiving circuit that is applied to a receiving section of a modem.

[Conventional technology]

In the receiving section of a conventionally known modem, the received signal is converted from analog to digital, and then a decoded output is obtained by a Viterbi decoder.

An example of a receiving section of a modem having such a configuration is shown in FIG. 3, divided by function. Here, automatic gain control circuit (AGC) 411. Demodulator (DEM) 413.
Roll-off filter (RoF) 415. Automatic equalizer (
AEQ)417. II transmission automatic phase control section (CAPC)
420 and a Viterbi decoder 430.

Here, the received signal (analog signal) introduced into this modem via the analog line is first gain compensated by the automatic gain control circuit 411.

The output signal (analog signal) gain-compensated by this automatic gain control circuit 411 is sampled and demodulated by a demodulator 413, and during analog-to-digital conversion, the influence of aliasing in the demodulator 413 is removed by a roll-off filter 415. Remove by. This demodulator 413
．． The digital signal obtained by demodulation by the roll-off filter 415 is a signal on the baseband, and is supplied to the automatic equalizer 417 after being compressed. Here, distortions caused by various line characteristics are compensated for.

That is, the automatic gain control circuit 411 compensates for signal amplitude, the roll-off filter 415 compensates for code amount interference, and the automatic equalizer 417 compensates for static characteristics (frequency characteristics, delay characteristics, etc.).

However, line characteristics change dynamically. For example, chiaria jitter will be present in the demodulated received signal 418. Such dynamic fluctuations cannot be compensated for by the above-described circuit alone, so even if the demodulated received signal 418 is supplied as is to the jumpy decoder 430, an error will occur in the decoding result. For this purpose, a jitter corrector IB421 is installed between the automatic equalizer 417 and the Viterbi decoder 430.
A CAPC (I wave automatic phase control unit) 420 including a hard decision circuit 425 is interposed.

In this CAPC 420, the demodulated received signal 418 obtained from the automatic equalizer 417 is first processed by the jitter correction circuit 421.
supplied to Here, jitters.

After the offset etc. are removed, the corrected output signal 42
3 is supplied to the hard decision circuit 425 at the next stage. In this hard decision circuit 425, a hard decision is made on the receiving point, and a decision data output signal 427 representing the hard decision point as a result of the decision is made.
is provided to the Viterbi decoder 430. Note that this Viterbi decoder 430 includes a hard decision circuit 425
The decoding output signal 431 is decoded based on the hard decision point by
It is designed to be supplied to

Incidentally, in order to perform necessary jitter control in the CAPC 420, the convenient fixed point output from the hard decision circuit 425 is fed back to the jitter correction circuit 421 as a sick control signal 429.

In this way, by controlling the phase based on the jitter control signal 429 from the hard decision circuit 425, correction for phase changes caused by fluctuations in dynamic characteristics can be taken.

Since high speed is required for jitter tracking in the CAPC 420, the decision output of the Viterbi decoder 430 has an output delay of several symbols, which cannot be used for jitter control in the jitter correction circuit 421. Therefore, the hard decision circuit 4
25 is provided to supply a hard decision output without phase delay to the jitter correction circuit 421.

[Problem to be solved by the invention]

In the receiving section of the conventional modem described above, the Viterbi decoder 430 performs decoding based on the hard-decision output from the hard-decision circuit 425.

However, if this Viterbi decoder does not use hard decision points, it is necessary to omit the hard decision circuit 425.

Therefore, it is no longer possible to obtain the jitter control signal 429 without symbol delay, and in a modem receiving circuit having the CAPC 420, a situation has arisen in which the CAPC cannot perform its original function.

The present invention was created in view of these points, and even if the Viterbi decoder does not use hard decision points, the C
The purpose of this invention is to provide a modem receiving circuit that allows APC to function.

[Means to solve the problem]

FIG. 1 is a basic block diagram of a modem receiving circuit according to the present invention.

In the figure, the modem receiving circuit according to the invention includes a carrier automatic phase control means 115 and a Viterbi decoder 119.

This carrier wave automatic phase control means 115 controls the received demodulated signal 1
11, performs jitter correction, and outputs an automatically phase-controlled reception code output signal 113. Also, the Viterbi decoder 1
19 receives the received code output signal 113 and outputs a decoded output signal 117.

The Viterbi decoder 119 includes branch metric calculation means 1
21, path memory 123, and path trace control means 1
25 and a trace memory 127.

Branch metric calculation means 121 calculates a branch metric based on received code output signal 113.

The path memory 123 includes branch metric calculation means 1.
Data of the minimum path metric based on the branch metric calculated by 21 is stored.

The hash trace llJ control means 125 includes the path memory 123.
Path tracing is performed based on the data stored in .

The trace memory 127 includes the path trace control means 12.
The results of path tracing according to No. 5 are stored sequentially according to symbols.

Therefore, as a whole, data based on the most recent symbol is fed back from the data in the trace memory 127 obtained during decoding for jitter correction in the carrier automatic phase control means 115.

[For production]

The branch metric calculation means 121 included in the Viterbi decoder 119 is supplied with the received code output signal 113 obtained by jitter-correcting the received demodulated signal 111 by the carrier automatic phase control means 115, and the received code output signal 1
The branch metric is calculated based on 13. Minimum path metric data based on this calculated branch metric is stored in the path memory 123.

Based on the data stored in the path memory 123, the path trace control means 125 performs path tracing, and the path trace results are stored in the trace memory 127 in sequence according to the symbols.

In addition to the data stored in the trace memory 127, data based on the most recent symbol is fed back to the carrier automatic phase control means 115. Based on the feedback data, carrier wave automatic phase control means 115 performs jitter correction.

In the present invention, data based on symbols near JFT is obtained from data in the trace memory 127 obtained during decoding, and jitter correction is performed in the carrier automatic phase control means 115, so that Viterbi decoding Even if the device 119 does not use hard decision points, the carrier wave automatic phase control section can perform its original function.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a modem receiving circuit in one embodiment of the present invention.

(1) Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The received demodulated signal 111 corresponds to the received demodulated signal 418.

The received code output signal 113 corresponds to the received code signal 227.

The carrier wave automatic phase control means 115 corresponds to a CAPC (carrier wave automatic phase control unit) 220.

The decoded output signal 117 corresponds to the decoded output signal 253.

Viterbi decoder 119 corresponds to Viterbi decoder 230.

The branch metric calculation means 121 corresponds to the distributor 233.

Path memory 123 corresponds to path memory 249.

Path tracing system? The 3111 means 125 corresponds to the path trace control section 243.

Trace memory 127 corresponds to trace memory 251.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

The overall configuration of the modem receiving circuit in the embodiment of the present invention is the same as that shown in FIG. 3. A distinctive feature of the embodiment of the present invention is the method of supplying the jitter control signal to the jitter correction circuit 421. Therefore 1. The same reference numerals as in FIG. 3 indicate corresponding circuit sections, and detailed explanation thereof will be omitted.

In FIG. 2, the demodulated received signal 4 is demodulated by the demodulator 413 shown in FIG.
18 is supplied to the jitter correction circuit 421 within the CAPC 220. This CAPC 220 (jitter correction circuit 421
) is output from the Viterbi decoder 2.
30.

In this Viterbi decoder 230, the received code signal 22
A branch metric signal 231 representing the branch metric calculated based on AC3 is sent from the distributor 233 to AC3.
(adder, comparator, selector) circuit 235. The AC3 circuit 235 adds the branch metric calculated by the distributor 233 and the path metric one symbol before, and supplies the summed output path metric signal 237 to the minimum path metric detection section 239 .

In addition, the path select signal 2 representing the maximum likelihood path selected by the comparison of path metrics in the AC3 circuit 235
41 is supplied to the path trace control unit 243.

Based on the minimum path metric determined by the minimum path metric detection section 239, the subset calculation section 245 provides the path trace control section 243 with a subset signal 247 representing the subset group having the minimum path metric.

This path trace control unit 243 is applied with a path memory length signal and other information, and based on these information, the path trace control unit 243 stores path selection data based on the path selection signal 241 in the path memory 249. . Further, the path trace control unit 243 writes the path trace result into the trace memory 251 to obtain a decoded output signal 253.

By the way, the trace memory 251 included in the bikubi decoder 230 sequentially stores data regarding past reception points over several symbols. Therefore, since the latest (one symbol previous) data is stored in the first stage memory element of this trace memory 251, the data stored in the first stage memory element is jitter controlled. As signal 229, CAPC 220 (
jitter correction circuit 421).

As a result, the CAPC 220 (jitter correction circuit 421
) is not delayed by several symbols, but is based on data one symbol before.

Therefore, even if the Viterbi decoder 230 that does not use hard decision points for decoding is connected to the next stage of the CAPC 220 (jitter correction circuit rlf!! 421) in the receiving section of the modem, the jitter control signal 229 without symbol delay is CAPC220
(jitter correction circuit 421), and CAPC 220 in the modem receiving circuit performs its original function.

-1-Kazuaki Kou-qheneTomokiIn addition, in ``Correspondence between Examples and Figure 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily guess that the present invention is not limited to this and that there are various modifications 84M.

〔Effect of the invention〕

As mentioned above, according to the present invention, data based on the most recent symbol is obtained from the path trace data obtained during decoding, and jitter correction is performed using the carrier automatic phase control means. Even if the Viterbi decoder that decodes the corrected received code is not based on hard decision points, the carrier automatic phase control section can still perform its original function, so it is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of a modem receiving circuit according to the present invention, Fig. 2 is a block diagram showing the configuration of a modem receiving circuit according to an embodiment of the present invention, and Fig. 3 is a block diagram showing a conventional modem receiving circuit. be. In the figure, 111 is a received demodulated signal, 113 is a received code output signal, 115 is a carrier automatic phase control means, 117 is a decoded output signal, 119 is a Viterbi decoder, 121 is a branch metric calculation means, 123 is a path memory, and 125 is a Path trace control means, 127 is a trace memory, 220.420 is a CAPC. 227 is a received code signal, 229.429 is a jitter control signal, 230.430 is a Viterbi decoder, 231 is a branch metric link signal, 233 is a distributor, 243 is a path trace control section, 249 is a path memory, 251 is a trace memory , 253 is a decoded output signal, 411 is an automatic gain control circuit, 413 is a demodulator, 415 is a roll-off filter, 417 is an automatic decoder, 418 is a demodulated received signal, 421 is a jitter correction circuit, and 425 is a hard decision circuit. be.

Claims (1)

[Claims] (1) A carrier wave automatic phase control means (115) that receives the received demodulated signal (111), performs jitter correction, and outputs an automatically phase-controlled received code output signal (113), and the received code output signal (113). The decoded output signal (117
), the Viterbi decoder (119) includes branch metric calculation means (12) that calculates a branch metric based on the received code output signal (113).
1), a path memory (123) in which data of a minimum path metric based on the branch metric calculated by the branch metric calculation means (121) is stored, and a path metric based on the data stored in the path memory (123) path tracing control means (125) for performing path tracing;
), and a trace memory (127) in which the results of the path trace by the path trace control means (125) are sequentially stored according to symbols, and data based on the latest symbols in the trace memory (127) are stored in the trace memory (127). The carrier wave automatic phase control means (11
5) A modem receiving circuit characterized in that it is configured to provide feedback for jitter correction.