JPH0217842U - - Google Patents

Info

Publication number
JPH0217842U
JPH0217842U JP1988095378U JP9537888U JPH0217842U JP H0217842 U JPH0217842 U JP H0217842U JP 1988095378 U JP1988095378 U JP 1988095378U JP 9537888 U JP9537888 U JP 9537888U JP H0217842 U JPH0217842 U JP H0217842U
Authority
JP
Japan
Prior art keywords
semiconductor device
bonding pad
polycrystalline silicon
silicon layer
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988095378U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988095378U priority Critical patent/JPH0217842U/ja
Publication of JPH0217842U publication Critical patent/JPH0217842U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07553—Controlling the environment, e.g. atmosphere composition or temperature changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例を示す断面図、第２図
は従来の配線図である。 １……半導体基板、２，４……絶縁層、３……
多結晶シリコン層（ポリシリ層）、５……パツド
配線層、６……カバー層、７……ボンデイングワ
イヤー。 FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a conventional wiring diagram. 1... Semiconductor substrate, 2, 4... Insulating layer, 3...
Polycrystalline silicon layer (polysilicon layer), 5... Padded wiring layer, 6... Cover layer, 7... Bonding wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体装置のボンデイングパツドにおいて、該
ボンデイングパツドの周縁部下層に多結晶シリコ
ン層を設けたことを特徴とする半導体装置。 1. A semiconductor device comprising a bonding pad for a semiconductor device, wherein a polycrystalline silicon layer is provided below the periphery of the bonding pad.
JP1988095378U 1988-07-18 1988-07-18 Pending JPH0217842U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988095378U JPH0217842U (en) 1988-07-18 1988-07-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988095378U JPH0217842U (en) 1988-07-18 1988-07-18

Publications (1)

Publication Number Publication Date
JPH0217842U true JPH0217842U (en) 1990-02-06

Family

ID=31320037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988095378U Pending JPH0217842U (en) 1988-07-18 1988-07-18

Country Status (1)

Country Link
JP (1) JPH0217842U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268943A (en) * 1988-09-02 1990-03-08 Matsushita Electron Corp Semiconductor device
JPH05183006A (en) * 1992-01-06 1993-07-23 Nec Yamagata Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268943A (en) * 1988-09-02 1990-03-08 Matsushita Electron Corp Semiconductor device
JPH05183006A (en) * 1992-01-06 1993-07-23 Nec Yamagata Ltd Semiconductor device

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