JPH0217876U - - Google Patents
Info
- Publication number
- JPH0217876U JPH0217876U JP9623888U JP9623888U JPH0217876U JP H0217876 U JPH0217876 U JP H0217876U JP 9623888 U JP9623888 U JP 9623888U JP 9623888 U JP9623888 U JP 9623888U JP H0217876 U JPH0217876 U JP H0217876U
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plating
- wiring board
- printed wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 238000009713 electroplating Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Description
第１図は本考案の一実施例、第２図は従来の一
例の表面処理である。
図において、１は銅導体、２は鉛層、３は半田
層、６はフツトプリント、７はスルーホール、８
は銅箔、９は絶縁基板、５１は無電解銅鍍金、５
２は銅電気鍍金、５３は電気半田鍍金、５４は銅
エツチング、５５は導体パターン成形、５６はヒ
ユージング、５９は鉛電気鍍金、８１は銅鍍金層
である。
FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an example of conventional surface treatment. In the figure, 1 is a copper conductor, 2 is a lead layer, 3 is a solder layer, 6 is a footprint, 7 is a through hole, and 8
is copper foil, 9 is an insulating substrate, 51 is electroless copper plating, 5
2 is copper electroplating, 53 is electric solder plating, 54 is copper etching, 55 is conductor pattern forming, 56 is fusing, 59 is lead electroplating, and 81 is a copper plating layer.
Claims (1)
は半田コートが行われている印刷配線板において
、 該銅導体１上に鉛鍍金を施し鉛層２を設けた上
に、所定の半田鍍金処理或いは半田コート処理を
行い半田層３を作成させることを特徴とする印刷
配線板導体の半田被覆構造。[Scope of Claim for Utility Model Registration] In a printed wiring board in which solder plating or solder coating is performed on a patterned copper conductor 1, lead plating is applied on the copper conductor 1 and a lead layer 2 is provided. A solder coating structure for a printed wiring board conductor, characterized in that a solder layer 3 is created by performing a predetermined solder plating treatment or solder coating treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9623888U JPH0217876U (en) | 1988-07-20 | 1988-07-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9623888U JPH0217876U (en) | 1988-07-20 | 1988-07-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0217876U true JPH0217876U (en) | 1990-02-06 |
Family
ID=31321095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9623888U Pending JPH0217876U (en) | 1988-07-20 | 1988-07-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0217876U (en) |
-
1988
- 1988-07-20 JP JP9623888U patent/JPH0217876U/ja active Pending
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