JPH02179101A - Interconnection system for cross type microstrip line - Google Patents

Abstract

PURPOSE:To minimize the electric fluctuation of microstrip lines connected in crossing by using a chip capacitor between 2nd and 3rd microstrip lines in terms of high frequency. CONSTITUTION:In order to decrease the area crossed with a 1st microstrip line 2 and the electric interference between lines, plural internal electrode plates (c) in parallel with first couple of opposite faces are provided in the inside of a rectangular chip capacitor 50, a couple of external electrodes a, b are provided to 2nd couple of opposite faces, part of the internal electrode plate (c) is connected to one external electrode and the other internal electrode (c) is connected to the other external electrode. As the 2nd and 3rd microstrip lines 3,4 are coupled in terms of high frequency by the chip capacitor 50 to reduce the impedance mismatching between the 2nd and 3rd microstrip lines 3, 4, the change in the electric characteristic of the microstrip lines is minimized.

Description

[Detailed Description of the Invention] [Summary] Regarding a method of forming a line by connecting microstrip lines that intersect at right angles on one microstrip line, it is possible to reduce the electrical fluctuations of the cross-connected microstrip lines. The purpose of the present invention is to provide a cross-connection method for cross-type microstrip lines that can be minimized, and has a rectangular parallelepiped outer shape and has a plurality of internal electrode plates parallel to a first pair of opposing surfaces, and a second A chip capacitor having a pair of external electrodes on a pair of opposing surfaces, in which some internal electrode plates are connected to one external electrode and other internal electrode plates are connected to the other external electrode. A pair of opposing surfaces are parallel to the dielectric substrate, one and the other external electrodes are placed on the second and third microstrip lines, respectively, and the chip capacitors are used to connect the second and third microstrip lines. The microstrip lines are configured to be connected at high frequency.

[Industrial application field]

The present invention relates to a method of forming a line by connecting microstrip lines that intersect at right angles on one microstrip line.

Circuits having lines formed using microstrip lines are usually required to have high performance and good reproducibility.

Therefore, using multiple microstrip lines,
When forming a line by cross-connecting them, it is possible to reduce the interference between the cross-connected microstrip lines, where one influences the other, and also to reduce the change in coupling impedance between the microstrip lines being connected. It is necessary to do so.

[Prior Art] FIG. 3 is a diagram illustrating a conventional example. The conventional example shown in FIG. 3 is used in a microwave band of approximately 10 GHz, and includes one first microstrip line and two second microstrip lines that intersect at right angles. This circuit uses the third microstrip lines 3 and 4 to form a line.

The first to third microstrip lines 2 to 4 are
For example, a microstrip line made of a strip conductor is formed on a substrate l made of alumina ceramic, fused silica, or the like with a thickness of 0.5 to 2 mm.

Therefore, the second microstrip line straddles the first microstrip line 2 and intersects it at right angles. When connecting the third microstrip lines 3 and 4, one conventional method is to connect the first microstrip line with a gold wire (or gold ribbon) 5 as shown in FIG.
The second microstrip line 2 is straddled. A method of connecting the third microstrip lines 3 and 4 is used.

(Problem to be Solved by the Invention) As described above, using the gold wire (or gold ribbon) 5,
When the two microstrip lines 3 and 4 are connected at right angles to each other, this gold wire (or gold ribbon)
There is a possibility that the inductance component of 5 will affect the impedance of the two connected microstrip lines 3.4, resulting in impedance mismatch between the two connected microstrip lines 3.4.

Also, by crossing one microstrip line 2 with a gold wire (or gold ribbon) 5, the microstrip line 2 where the gold wire (or gold ribbon) 5 intersects can be created.
There may be more electrical interference.

Therefore, these factors cause large fluctuations in the electrical characteristics of the line formed by the microstrip line.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cross-connection method for cross-connected microstrip lines that can minimize electrical fluctuations in cross-connected microstrip lines.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the embodiment of the present invention shown in FIG. 1, 2 to 4 are first to third microstripes similar to those explained in FIG. 3, and 50 has a rectangular parallelepiped outer shape. This is a chip capacitor, and this rectangular parallelepiped chip capacitor 50 has a plurality of parallel internal electrode plates (C) on a first pair of opposing surfaces, and a pair of external electrodes (a) on a second pair of opposing surfaces. , (b), and is configured such that some internal electrode plates (C) are connected to one external electrode and other internal electrode plates (C) are connected to the other external electrode, and such a chip capacitor 50 , the third pair of opposing surfaces are parallel to the dielectric substrate l, and one and the other external electrode (
a) and (b) are placed on the second and third microstrip lines 3 and 4, respectively, and a chip capacitor 50 connects the second and third microstrip lines 3 and 4 with high frequency. By connecting the wires,
This is a means to solve this problem.

(Function) When connecting the rectangular parallelepiped chip capacitor 50 and the second and third microstrip lines 3.4 created on a line perpendicular to the first microstrip line 2, the second and third microstrip lines 3.4 are connected. In order to reduce the area where one microstrip line 2 intersects and reduce electrical interference between the lines, a plurality of internal electrode plates (C ),
A pair of external electrodes (a), (b) on the second pair of opposing surfaces
It has a structure in which some internal electrode plates (C) are connected to one external electrode, and other internal electrode plates (C) are connected to the other external electrode.

The chip capacitor 50 has a third pair of opposing surfaces parallel to the dielectric substrate 1, and one and the other external electrodes (a) and (b) are respectively connected to the second and third microstrip lines 3. 4, place it so that it is placed on top of the
By connecting the second and third microstrip lines 3.4 using the chip capacitor 50, the impedance mismatch between the second and third microstrip lines 3.4 is reduced. It becomes possible to minimize changes in the electrical characteristics of the line.

(Example) The gist of the present invention will be specifically explained below with reference to an example shown in FIGS. 1 and 2.

FIG. 2 shows a diagram illustrating an example of the structure of a chip capacitor according to the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

It is assumed that the first to third microstrip lines 2 to 4 of this embodiment shown in FIG. 1 are formed on a substrate 1 made of aluminum ceramic or the like as explained in FIG. 3.

Further, it is assumed that the first to third microstrip lines 2 to 4 of this embodiment are also used in the microwave band of approximately 10 GHz, as explained in FIG.

Note that FIG. 1(A) is a view of the intersection portion of this embodiment viewed from above, and FIG. 1(B) is a view showing the overall external configuration.

The chip capacitor 50 used in this embodiment is a discrete component that is not integrated or aggregated, and has a structure suitable for surface mounting.

As shown in Fig. 2, the structure is such that electrodes (a) and (b) are used at both ends of the rectangular parallelepiped, and the outer surface is made of, for example, ceramic (
d), and a plurality of electrode plates (C) are stacked on top of each other at regular intervals inside the electrode plate (C).

If this chip capacitor 50 is placed with the surface side of the rectangular parallelepiped
If the second and third microstrip lines 3 and 4 are connected by crossing them in a direction corresponding to the microstrip line 2, the coupling area and crossing area will become larger, which is a factor that increases the change in impedance. Become.

Therefore, in this embodiment, as shown in FIGS. 1A and 1B, the rectangular parallelepiped of the chip capacitor 50 is erected perpendicularly to the first microstrip line 2 and intersects with it.

That is, the surface of the internal electrode plate (C) of the chip capacitor 50 is perpendicular to the first microstrip line 2, and the electrodes (a) of the chip capacitor 50 are crossed.
and (b) are connected to the second and third microstrip lines 3 and 4 located on a straight line.

As a result, the second and third microstrip lines 3.
4 and the first microstrip line 2
It is possible to reduce the area of intersection with the

Therefore, the first microstrip line 2 and the second .
Electrical interference between the lines and the second and third microstrip lines 3 and 4 is reduced, and furthermore, it is possible to minimize changes in the coupling impedance between the connected second and third microstrip lines 3 and 4. becomes.

〔Effect of the invention〕

According to the present invention as described above, changes in the electrical characteristics of the microstrip line can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the present invention in detail, FIG. 2 is a diagram for explaining a configuration example of a chip capacitor according to the present invention, and FIG. 3 is a diagram for explaining a conventional example. In the figure, ■ is the board, 2 to 4 are the first to third microstrip lines, 5 is the gold wire (gold ribbon), 50 is the chip capacitor, and Hizuki Kinoto (Niakero Chip Container/7 Decay Threat) “J $ first ward te Δ
figure

Claims (1)

[Claims] In a cross-connection system between second and third microstrip lines (3, 4) provided on a dielectric substrate (1) with a first microstrip line (2) in between, It has a rectangular parallelepiped outer shape, has a plurality of internal electrode plates ((c)) parallel to the first pair of opposing surfaces, and has a pair of external electrodes ((a), (b) on the second pair of opposing surfaces. ), some internal electrode plates ((c)) are connected to one external electrode, and other internal electrode plates ((c)) are connected to the other external electrode (50). , a third pair of opposing surfaces are parallel to the dielectric substrate (1), and one and the other external electrodes ((a), (b)) are connected to the second and third microstrip lines (3), respectively. , 4), and the chip capacitor (50) connects the second and third microstrip lines (3, 4) at high frequency. Microstrip line connection method.