JPH02180032A - Manufacture of gaas mesfet - Google Patents

Abstract

PURPOSE:To form a gate electrode in self-alignment with a small width and to reduce a distance between the gate electrode and a source electrode by forming eaves by a resist and a metal electrode through etching and by forming the gate electrode thereafter. CONSTITUTION:An n-type GaAs active layer, an n<+>-GaAs layer and an n<+>- InGaAs layer are laminated through epitaxial growth on a surface of a semiinsulating GaAs substrate 10, and a metal electrode 11 which is a material of Schottky electrode is formed on the substrate 1. A photoresist 12 is formed on a surface of a metal electrode 11, etching for shaping an aperture of a width lis performed through exposure, and the metal electrode 11 is etched successively. Since the n<+>-type InGaAs layer and the metal electrode 11 are not alloyed, a section of the metal electrode 11 is etched to a lower part of the photoresist 12 to form a shape of eaves (section A). According to this constitution, a gate electrode 13 is shielded by the eaves of the resist 12 and an original width (l) is made smaller to (l'). Furthermore, a distance between a drain and a source of the metal electrode can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a GaAs MESFET.

<Conventional technology> MESFET using a compound semiconductor such as GaAs as a substrate
Field-effect transistors (field-effect transistors) are known to exhibit very good performance in ultra-high frequency and ultra-high speed signal processing, and the requirements for improving their performance are shortening the gate length, It is important to reduce the sheet resistance between drains.

Figures 2 (a) to (f) show the conventional MES FET! !
This figure shows the four-piece structure and its general manufacturing method.

In FIG. 2(a), an n-type Ga layer is formed on a semi-insulating GaAs substrate 1.
An As active layer 3 is formed by ion implantation.

Next, in Figure (b), a gate electrode 4 is formed on the n-type GaAs layer 2 to a thickness of about 2000 Å to 3000 Å.

Next, in the figure (c), an insulating layer 5 of SiO2 or the like is formed on the gate electrode 4 including the substrate.

Next, in figure (d), one reactive ion etching (RI
Step E) is performed to form a sidewall 6 made of an insulating layer, leaving only the side surfaces of the gate electrode.

Next, as shown in FIG. 3(e), metal electrodes 7 serving as a drain and a source are formed on the gate electrode including the substrate.

Apply resist.

Next, in the figure (f), the resist and metal electrode 7 on the gate electrode are removed.

Next, in the figure (g), the metal electrode 7 is subjected to alloying heat treatment.

Such a method is called sidewall-assisted short electrode technology.

<Problems to be Solved by the Invention> However, the above conventional manufacturing method has the following problems.

(2) The thickness of the metal electrode 7 cannot be made thicker than the gate electrode 4 (thickness 20008 to 30008). That is, the thickness of the metal electrode 7 is limited to the thickness of the gate electrode 4.

(2) Since the metal electrode 7 is thin, the beginning of the gate electrode 4 is unstable.

(2) The metal electrode layer 7 and the n-type GaAs layer 3 need to be alloyed, which requires a heat treatment process. Therefore, the metal electrode 7 is deformed and the pattern shape is deteriorated.

The present invention was made in order to solve the problems of the prior art described above, and it is possible to form a fine gate electrode in a self-aligned manner only by patterning the metal electrodes, and the distance between the metal electrodes (source, drain). can be shortened,
In addition, GaAs ME does not require a heat treatment process for metal electrodes.
The purpose of the present invention is to provide a method for manufacturing SFBT.

Means for Solving the Problems> The manufacturing method of the present invention is to solve the problems of the prior art described above.

An n-type GaAs active layer n-type G on a semi-insulating GaAs substrate.
a step of laminating an As layer and an n-type InGaAs layer;

a step of laminating a metal electrode on the substrate; and a step of applying a resist to the metal electrode, patterning it to form a groove, and exposing the metal electrode to the width of the groove.

etching the metal electrode;

The n-type I n Ga As layer, n + type GaAs
etching a portion of the n-type GaAs active layer; and forming a gate electrode on the n-type GaAs active layer using the resist as a mask.

It is characterized by including.

<Example> The present invention will be described below with reference to one drawing. Figure 1(a)-(
f> is a schematic process showing an example of the manufacturing method of the present invention.

(a) In the figure, n is formed on the surface of a semi-insulating GaAs substrate 1.
type GaAs active layer, n” GaAs layer, and n+In
GaAs layers 3 each having a thickness of about 500 Å are laminated by epitaxial growth.

(b) In the figure, a metal electrode (for example, Ti, WSix) which is a Schottky electrode material is placed on the substrate 1.

']'aSi, etc.) 11 is formed to a thickness of 1°008 to 2000° by sputtering, vapor deposition, etc. 'T' above
i.

Electrodes such as WSix and TaSi have the property of not reacting with the n+Tn-GaAs layer, and there is no need for 1-alloying.

(C) In the figure, a photoresist 12 is formed on the surface of the metal electrode 11, and the width is increased by exposure. Open window etching is performed, followed by etching of metal mold @11. When the metal is Ti, this etching can be easily carried out by using an HF-based etchant or by performing reactive ion etching (RIE). In addition, the window! width is 0
．． It is about 5 to 1°5 μm.

In this case, since the n+ type InGaAs layer and the metal electrode 11 are not alloyed, the metal electrode 11 portion is etched to the bottom of the photoresist 12, forming an eaves-shaped (part A).
is formed. Etching time is about 30 seconds.

(d) In the figure, citric acid is further used as an etching solution.
n+ ten-type nGaA using a mixture of H2O2 and water
The sN, n+ type GaAs layer and n type GaAs active layer are etched. In this case, the crystal orientation of the etched portion is formed so that it has a trapezoidal shape, for example, as shown in the figure (it does not necessarily have to be trapezoidal). In this case too, G a A
Since the s-layer and the metal electrode 11 are not alloyed, the metal electrode portion is formed in the shape of an eave (8 parts). Etching time is about 1 minute.

In the figure (e), a gate electrode 13 is formed by sputtering or vapor deposition from above the resist 12 including the window. As the material of the gate electrode 13, a Schottky electrode material such as Al, Ti, WSi, etc. is used. In this case, the gate electrode 13 is blocked by the eaves of the resist 12.

Starting width! of! - can be formed narrowly, reducing the risk of contact between the metal electrode and the gate electrode. Furthermore, the distance between the metal electrodes (drain, sos) can be narrowed compared to the conventional example.

(f) In the figure, the gate electrode material 13- on the resist and the resist 12 are removed, and the metal type t#! 11. Sauce on top 14. A ti lead for the drain 15 is formed.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, a metal electrode is formed on n''1nGaAs grown on a semi-insulating substrate, and etched to form a resist and a metal electrode. Since the gate electrode is formed after forming the eaves, the window can be formed in a self-aligned manner with a width narrower than that of the initially formed window.

Furthermore, since the space between the gate electrode and the source electrode becomes narrower, the sheet resistance can be lowered.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing an embodiment of the GaAs MESFET manufacturing method of the present invention, and FIG. 2 is a diagram showing a schematic process of a conventional manufacturing method. 10... Semi-insulating GaAs, 11... Metal electrode, 1
2...Resist, 13...Gate electrode, 14...
sauce. Diagram

Claims (1)

[Claims] An n-type GaAs active layer, n^+, on a semi-insulating GaAs substrate.
A step of laminating a type GaAs layer and an n^+ type InGaAs layer, a step of laminating a metal electrode on the substrate, a resist is applied to the metal electrode, patterning is performed to form a groove, and the width of the groove is filled with the metal electrode. a step of exposing the electrode; a step of etching the metal electrode; a step of etching a part of the n^+ type InGaAs layer, the n^+ type GaAs layer and the n type GaAs active layer; and using the resist as a mask. A method for manufacturing a GaAs MESFET, comprising: forming a gate electrode on the n-type GaAs active layer.