JPH02181282A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To directly use the software which is described with an instruction of an emulation CPU by designating the action mode of the CPU at an interruption process via an action mode designating circuit. CONSTITUTION:When an interruption process request is produced, an interruption control circuit 2 outputs an interruption process request signal 7 to a CPU 3. The CPU 3 accepts the process request in the final timing for execution of an instruction and outputs an interruption process acceptance signal 8 to the circuit 2 and an action mode designating circuit 12. In this case, the circuit 12 outputs a decoder switch signal 40 to the CPU 3 and at the same time outputs a CPU designating signal 14 to the CPU 3 based on an action mode designating signal 15 which is inputted in response to the level of an external terminal 11. The CPU 3 switches its action mode between the native and emulation modes based on both signals 40 and 14 and executes an interruption process.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides an interrupt processing system for a single-chip microcomputer that has a computer function and a central processing unit (hereinafter referred to as CPU) emulation function on a single semiconductor substrate. This invention relates to a single-chip microcomputer that can specify a CPU that performs the following steps.

[Conventional technology]

In recent years, advances in LSI manufacturing technology have led to higher integration in the field of single-chip microcomputers.
The cost per unit function is also decreasing significantly.

Along with this trend, the fields of use of single-chip microcomputers have expanded, and a huge amount of software has been accumulated.

In order to effectively utilize the software assets mentioned above,
Although it is necessary to use a CPU that is compatible in the architecture, it may be impossible to use a CPU that is compatible at the instruction code level due to various conditions such as demands for improved performance and low cost. .

Such cases have conventionally been solved by incorporating a built-in function to emulate command functions and allowing programs created for past CPUs to be used as they are.

That is, assuming that the CPU in native mode is CPUI and the CPU in emulation mode is CPU2, the CPU 2 switches from native mode to emulation mode and executes the instruction code of CPU2. In other cases, execution is performed in the CPU1 mode (native mode).

In this way, the past software assets created for the CPU 2 are effectively utilized, and the man-hours for creating new software are reduced.

At this time, there is a problem in which mode the interrupt processing should be performed, but since conventional single-chip microcontrollers were configured to execute in native mode, interrupt processing programs written using CPU2 instructions cannot be used. First, it has the disadvantage that additional man-hours are required to create the software because it needs to be rewritten using CPU commands. An example of a conventional single-chip microcomputer will be described below with reference to the block diagram of the microcomputer shown in FIG.

First, the constituent elements will be explained.

In FIG. 5, CPU3 is a central processing unit.

Memory section 9 is a read-only memo! J ROM(Rea
dOnly Memory) and memory RAM (Random Access) that can be read and written.
Memory) and is used as a working area when storing user programs and processing data.

The internal bus 6 is a bus that transfers addresses and data in a time-division manner.

Main decoder 4 is an instruction decoder used in native mode. Sub-decoder 5 is an instruction decoder used in emulation mode.

The CPU 3 fetches the instructions stored in the memory section 9 via the internal bus 6, decodes them with the instruction decoder 4 when in native mode, and decodes them with the sub-decoder 5 when in emulation mode. Execute commands.

The peripheral section 10 is an input/output port for data communication with the outside of the chip, and has the function of outputting data on the internal bus 6 to the outside of the chip and outputting input data from outside the chip to the internal bus 6.

The interrupt control circuit 2 causes the CPU to execute interrupt processing in accordance with an external interrupt request signal 35 input from outside the chip. That is, when the interrupt control circuit 2 receives the interrupt request signal 35 from outside the chip, it outputs the interrupt processing request signal 7.
is output to CPU3. At this time, the CPU 3 outputs a signal 8 to accept the interrupt process, and executes the interrupt process.

The operation will be explained using the above components.

The CPU 3 reads the instruction code from the memory section 9 and fetches it via the internal bus 6. The fetched instruction code is decoded by the main decoder 4 in the native mode, and is executed after being decoded by the sub-decoder 5 in the emulation mode. When the instruction execution is completed, the next instruction is fetched from the memory unit 9 and the above-described processing is continued.

Switching of the instruction decoder is performed by a special instruction of the CPU.

That is, by executing a special instruction of the CPU, the instruction decoder is switched to the sub-decoder 5, and the program is executed in emulation mode. When the execution of the program in the emulation mode is finished, the main decoder 4 is switched to the main decoder 4 by a special instruction, and the program is executed in the native mode.

The switching of the CPU operation mode by commands is described in detail in page 114-pH6 of the data book "V Series Microprocessors/Peripherals 1988" published by the Semiconductor Marketing Headquarters of NEC Corporation.

Next, the operation during interrupt processing will be explained.

When an interrupt request is generated from outside the chip, the interrupt control circuit 2 outputs an interrupt processing request signal 7 to the CPU 3. The CPU 3 accepts the interrupt processing request at the final timing of the instruction execution process, and outputs a signal 8 when the interrupt processing is accepted. At this time, regardless of the operating mode of the CPU, the CPU 3 sets the instruction decoder to the main decoder 4 and executes interrupt processing in the native mode. When returning from interrupt processing (for example, when executing a RETI instruction), the operation mode returns to the one before the interrupt processing.

In the single-chip microcomputer mentioned above,
Interrupt processing is always performed in native mode, so even if a program created using emulation mode CPU instructions can be used as is, it is necessary to create a new interrupt control program using native mode CPU instructions. . In addition, inspection must be performed, which increases the number of man-hours involved in creating new software. This results in weakening the effect of having a built-in emulation mode.

[Problem to be solved by the invention]

As mentioned above, in conventional single Chisso microcomputers, the native mode is always used when executing interrupt processing, so it is necessary to rewrite programs written using emulation CPU instructions using native mode CPU instructions. Taking into consideration the depacking and inspection work of the program, there was a drawback that a huge number of man-hours were required.

[Means to solve the problem]

The single-chip microcomputer according to the present invention is a single-chip microcomputer that integrates computer functions on a single semiconductor substrate and has a built-in central processing unit emulation function, and is equipped with a 1-bit flag that turns on during interrupt processing and has an external terminal. The CPU includes an operation mode designation circuit that designates an operation mode of the central processing unit according to an input signal from the central processing unit, and the operation mode designation circuit designates the operation mode of the central processing unit during interrupt processing. . Or, in a synchronized F-Tub microcomputer that integrates computer functions on a single semiconductor substrate and has a built-in central processing unit emulation function, an operation that is operated by a 1-bit flag that is turned on during interrupt processing and a command from the central processing unit. The present invention is characterized in that it has a built-in operation mode designation circuit consisting of a mode designation flag, and the operation mode designation circuit designates the operation mode during interrupt processing.

Thus, the single-chip microcomputer according to the present invention has a built-in function that can specify the operating mode of the CPU during interrupt processing, and by specifying the CPU that performs interrupt processing as the emulation CPU as necessary, Software written using emulation CPU instructions can be used as is, and the number of steps required to create software can be significantly reduced.

〔Example〕

FIG. 1 is a block diagram of a single Nisso microcomputer according to a first embodiment of the present invention.

The single Chisso microcomputer according to the first embodiment of the present invention is similar to the conventional example shown in FIG. There is no difference. Therefore, the operation mode designation circuit will be mainly explained below with reference to FIG.

In this embodiment, the explanation will be given assuming that there is one emulation CPU.

The single-chip microcomputer of the first embodiment shown in FIG. 1 has a configuration in which a function for specifying the operating mode of the CPU during interrupt processing is added to a conventional single-chip microcomputer.

The external terminal 11 is a terminal used to specify the CPU operation mode for interrupt processing from outside the chip, and outputs an operation mode designation signal 15 to the operation mode designation circuit 12.

The CPU 3 issues a return command (for example, R,
When the execution of the ETI command is completed, a clear signal 13 is output to the operation mode designation circuit 12.

The operation mode designation circuit 12 outputs a decoder switching signal 40 to the CPU 3 during interrupt processing, and also outputs a CPU designation signal 14 to the CPU 3 according to the operation mode designation signal 15.
3 to specify the operation mode during interrupt processing.

The operation will be explained below.

When an interrupt processing request occurs, the interrupt control circuit 2 outputs an interrupt processing request signal 7 to the CPU 3.

The CPU 3 accepts the interrupt processing request at the final timing of instruction execution, and outputs a signal 8 to the interrupt control circuit 2 and the operation mode designation circuit 12 in response to the interrupt processing request.

At this time, the operation mode designation circuit 12 outputs the decoder switching signal 40 to the CPU 3, and also outputs the CPU designation signal 14 to the CPU 3 in accordance with the operation mode designation signal 15 input according to the level of the external terminal 11. CPU
3 is a decoder switching signal 40 and a CPU designation signal 1
4, the operating mode of the CPU is switched to native mode or emulation mode, and interrupt processing is executed.

When executing a return instruction from interrupt processing, the CPU 3 returns to the operating mode before execution of the interrupt processing and continues the instruction processing.

It is assumed that the CPU 3 switches the instruction decoder according to the CPU designation signal 14 only while the decoder switching signal 40 is being output.

That is, decoder switching signal 40=1. When the CPU designation signal 14=1, processing is performed in the sub-decoder 5, and the decoder switching signal 40=1. When the CPU designation signal 14=0, the main decoder 4 performs processing.

Next, the operation mode designation circuit 12 will be explained using FIG. 2.

First, the constituent elements will be explained.

The buffer 18 is a Schmidt type buffer,
After amplifying the operation mode designation signal 15, it is output to an AND gate 16. The 1-bit flag 17 is a flag that is set by the signal 8 when interrupt processing is accepted and reset by the interrupt processing end signal 13, and outputs the stored value to the AND gate 16 and outputs the decoder switching signal 40 to the CPU 3. do.

The AND gate 16 is a two-man power AND gate that receives the flag 17 and the output of the buffer 18, and outputs the CPU designation signal 14.

The interrupt processing operation will be explained below using the above components.

When the CPU 3 outputs the interrupt processing acceptance signal 8, the flag 17 is set and the decoder switching signal 40 is output to the CPU 3.

At this time, the operation mode designation signal 15 is amplified by the buffer 18 and then output to the AND gate 16.

Since the output of the flag 17 is 1, the AND gate 16 directly uses the output of the buffer 18 as the CPU designation signal 14.
Output to PU3.

Therefore, since the decoder switching signal 40 is output to the CPU 3, the CPU 3 executes interrupt processing in emulation mode or native mode according to the input level of the external terminal 11.

That is, when external terminal 11=o, operation mode designation signal 1
Since 5=0, execution is performed in native mode, and when external terminal 11=1, operation mode designation signal 15=1, execution is performed in emulation mode.

When executing the return instruction from interrupt processing, the CPU 3 outputs the interrupt processing end signal 13 to the operation mode designation circuit 12, resets the flag 17 to set the decoder switching signal 40 to O, and then outputs the interrupt processing end signal 13 to the operation mode designation circuit 12, and then sets the decoder switching signal 40 to O by resetting the flag 17. It will return to the operating mode and continue processing instructions.

As described above, in the single-chip microcomputer according to the first embodiment, by adding an operation mode designation circuit consisting of a simple configuration, it is possible to designate the CPU that performs interrupt processing, and by setting the external terminal to high. By doing so, it is possible to use an interrupt processing program written using emulation CPU instructions as is.

Therefore, the accumulated software can be used as is, which improves the effectiveness of the built-in emulation mode.

Further, even if it is desired to use a native CPU program for interrupt processing, by setting the external terminal to low, the processing can be performed by the native mode CPU, and a flexible configuration can be realized.

Although the first embodiment has been described assuming that there is one CPU that can be emulated, it is also possible to consider a case where there is a plurality of CPUs.

Next, a second embodiment of the single-chip microcomputer according to the present invention will be described with reference to FIG.

FIG. 3 is a block diagram of a single-chip microcomputer according to a second embodiment of the present invention.

The single-chip microcomputer according to the second embodiment of the present invention differs from the first embodiment in that the CPU that performs interrupt processing is specified not by the input level of the external terminal but by the instructions of the CPU in native mode. This is different from the single-chip microcontroller involved. This will be explained below using FIG. In this embodiment, the number of CPUs that can be emulated is one.

The single-chip microcomputer of the second embodiment shown in FIG. 3 has a configuration in which a function for specifying the operating mode of the CPU during interrupt processing is added to a conventional single-chip microcomputer.

The CPU 3 outputs a set signal 20 to the operation mode designation circuit 32 when executing a set command, and outputs a reset signal 21 to the operation mode designation circuit 32 when executing a reset command.

The CPU 3 issues a return instruction (for example, RE
When the execution of the TI instruction is completed, a clear signal 13 is output to the operation mode designation circuit 32.

The operation mode designation circuit 32 outputs a decoder switching signal 40 during interrupt processing and also outputs a CPU designation signal 14 to the CPU 3 to designate the operating mode of the CPU during interrupt processing.

The interrupt processing operation will be explained below.

When an interrupt processing request occurs, the interrupt control circuit 2 outputs an interrupt processing request signal 7 to the CPU 3.

The CPU 3 accepts the interrupt processing request at the final timing of instruction execution, and outputs a signal 8 to the interrupt control circuit 2 and the operation mode designation circuit 32 in response to the interrupt processing request.

The operation mode designation circuit 32 receives a decoder switching signal 40
and outputs a CPU designation signal 14 to the CPU 3. CPU
3 is a decoder switching signal 40 and a CPU designation signal 14
Accordingly, decoder switching signal 40=1. In native mode when CPU designation signal 14 = 0, and when decoder switching signal 40 = 1. When CPU designation signal 14=1, interrupt processing is executed in emulation mode.

The CPU 3 issues a return command (for example, RET) from interrupt processing.
After outputting the interrupt processing end signal 13 to the operation mode specifying circuit 32 when executing the I instruction, the operation mode returns to the operation mode before execution of the interrupt processing and continues the instruction processing.

It is assumed that the CPU 3 switches the instruction decoder according to the CPU designation signal 14 only while the decoder switching signal 4ρ is being output.

Next, the operation mode designation circuit 32 will be explained using FIG. 4.

First, the constituent elements will be explained.

The flag 22 is a 1-bit flag that is set by the set signal 20 and reset by the reset signal 21, and outputs the stored value to the AND game 16. The 1-bit flag 17 is a flag that is set by the signal 8 when interrupt processing is accepted and reset by the interrupt processing completion signal, and outputs the stored value to the AND gate 16 and also outputs the stored value to the CPU 3 as the decoder switching signal 40. Output.

The AND gate 16 is a two-man power AND gate that receives the outputs of the flag 17 and the flag 22, and outputs the CPU designation signal 14.

The interrupt processing operation will be explained below using the above components.

When the CPU 3 outputs the interrupt processing acceptance signal 8, a flag 17 is set and a decoder switching signal 40 is output to the CPU 3.

At this time, the stored value of flag 22 is AND'y'-to16
is output to. Since the output of the flag 17 is 1, the AND gate 16 outputs the output of the flag 22 as it is to the CPU 3 as the CPU designation signal 14.

Therefore, since the decoder switching signal 40 is output to the CPU 3, the CPU 3 operates according to the stored value of the flag 22.
Switch.

For example, if the flag 22 has been previously set by executing a set instruction in native mode, it will operate in emulation mode, and if the flag 22 has been reset by executing a reset instruction, it will operate in native mode.

In other words, it is possible to easily set in which CPU operation mode interrupt processing is to be executed by executing the special instruction.

Therefore, if you want to use a program already created for the emulation CPU as an interrupt processing program,
Settings can be easily made by simply executing a set command in native mode in advance.

Furthermore, when using a newly created program for a native CPU as an interrupt processing program, it is sufficient to execute a reset instruction in the native mode in advance.

The CPU 3 outputs the interrupt processing end signal 13 to the operation mode designation circuit 32 when executing the return instruction from the interrupt processing,
After resetting the flag 17 and turning off the decoder switching signal 40, the operation mode returns to the one before execution of the interrupt processing,
Continue instruction processing.

As described above, in the single-chip microcomputer according to the second embodiment, by adding an operation mode designation circuit having a simple configuration, the native CPU can be used without using external terminals for designating the CPU operation mode. The CPU mode in which interrupt processing is to be performed can be specified by the instruction, and an interrupt processing program written using emulation CPU instructions can be used as is.

Therefore, the accumulated software can be used as is, which improves the effectiveness of the built-in emulation mode.

Furthermore, interrupt processing can be performed by a native mode CPU, and a flexible configuration can be realized.

Although the second embodiment has been described assuming that there is one CPU that can be emulated, a plurality of CPUs can be easily supported by expanding the configuration of the operation mode designation circuit.

〔Effect of the invention〕

As explained above, in the present invention, by incorporating an operation mode designation circuit with a simple configuration, it is possible to designate the CPU that performs interrupt processing, and emulation that could not be used because the CPU was conventionally fixed to native mode. Interrupt processing programs that have already been created for the CPU can be used as is, and native mode CPUs
It is possible to reduce the number of man-hours required to create a new interrupt processing program using these instructions. Furthermore, there is no need to check the program, which is very effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a single-chip microcomputer in the first embodiment of the present invention, FIG. 2 is a block diagram of an operation mode designation circuit in the first embodiment, and FIG. 3 is a block diagram of a single-chip microcomputer in the second embodiment. A block diagram of a chip microcomputer, FIG. 4 is a block diagram of an operation mode designation circuit in the second embodiment, and FIG. 5 is a block diagram of a conventional single-chip microcomputer. 2...Interrupt control circuit, 3...CPU, 4...
Main decoder, 5...Sub decoder, 6...
...Internal bus, 7...Interrupt processing request signal, 8...Interrupt processing acceptance signal, 9...
...Memory section, 10...Peripheral section, 11...
...External terminal, 12.32...Operating mode designation circuit, 13...Interrupt processing end signal, 14...
...CPU designation signal, 15 ...Operating mode designation signal, 20 ...Set signal, 1 ...Clear signal, 0 ...Decoder switching signal .

Claims (2)

[Claims] (1) Integrating computer functions on a single semiconductor substrate,
In a single-chip microcomputer with a built-in central processing unit emulation function, an operation mode designation circuit includes a 1-bit flag that is turned on during interrupt processing and designates the operation mode of the central processing unit according to an input signal from an external terminal. 1. A single-chip microcomputer, characterized in that the operation mode designation circuit specifies an operation mode of the central processing unit during interrupt processing. (2) Integrating computer functions on a single semiconductor substrate,
In a single-chip microcomputer with a built-in emulation function for a central processing unit, an operation mode designation consisting of a 1-bit flag that is turned on during interrupt processing and a flag for specifying the operation mode of the central processing unit that is operated by instructions from the central processing unit. 1. A single-chip microcomputer comprising a built-in circuit, the operation mode designation circuit designating an operation mode of the central processing unit during interrupt processing.