JPH02181442A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a gate electrode deviated to the source region side simply by implanting an impurity in high concentration while using an inorganic material film left on a sidewall section on the drain region side of the gate electrode and the gate electrode as masks. CONSTITUTION:A gate electrode 42 composed of a high melting-point metal is formed onto a semiconductor substrate 1 to which an operating layer 2 is shaped previously. An inorganic material film 21 is applied, a resist pattern 13 convering the inorganic material film 21 on the drain region side of the gate electrode 42 is formed, the inorganic material film 21 is removed while employing the resist pattern 13 as a mask, the resist pattern 13 is taken off, and the inorganic material film 21 is left on a sidewall section on the drain region side of the gate electrode 42. An impurity is implanted in high concentration while using the gate electrode 42 and the inorganic material film 21 left on the sidewall as masks, thus forming a source region 3 and a drain region 4 to the semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and in particular to a method for manufacturing a field effect transistor (Schottky gate type field effect transistor).
MESFET).

[Conventional technology]

In MESFETs, the distance between the n-layer on the drain side and the gate electrode is wider than the distance between the n-layer on the source side and the gate electrode, which increases the drain breakdown voltage while keeping the series resistance at a small value. It is being considered that the drain conductance can be lowered by increasing the drain conductance. As a method for manufacturing MESFET with such an asymmetric structure,
For example, a device using a dummy gate with a multilayer structure is already known (Japanese Patent Laid-Open No. 194781/1981).

[Problem to be solved by the invention]

However, in the above-mentioned method, manufacturing of the asymmetric dummy gate structure is complicated, and there are problems to be solved such as poor reproducibility.

[Means to solve the problem]

The method for manufacturing a field effect transistor according to the present invention includes a first step of forming a gate electrode made of a high melting point metal on a semiconductor substrate on which an active layer has been formed in advance, and a step of forming a gate electrode made of a high melting point metal after depositing an inorganic material film. A second step involves forming a resist pattern covering the inorganic material film on the drain region side, and removing the inorganic material film using this resist pattern as a mask, and removing the resist pattern and etching the inorganic material film by reactive ion etching or the like. A third step involves etching to leave an inorganic material film on the side wall of the gate electrode on the drain region side, and a third step in which impurities are implanted at a high concentration using this inorganic material film and the gate electrode as a mask, and the source and drain regions are placed on the semiconductor substrate. and a fourth step of forming.

[Effect]

According to the present invention, an inorganic material film is not formed on the side wall of the gate electrode on the source region side, but is formed on the side wall of the gate electrode on the drain region side. Source/drain regions are formed by ion implantation.

Therefore, it is possible to realize a gate electrode shifted toward the source region.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing the manufacturing process of the embodiment.

First, a semiconductor wiping plate 1 made of, for example, GaAs is prepared, a photoresist film 11 is formed by a spin code method, etc., and patterned by photolithography. and,
An n-type impurity is ion-implanted through this patterned photoresist film 11 to form an n-type active layer 2 (as shown in FIG. 1(a)).

Next, the photoresist film 11 is removed by immersion in acetone or ashing, and a gate electrode material film 41 made of a high-melting point metal is deposited using a vacuum evaporation method or a sputtering method. Apply membrane 12. Then, this resist film 12 is patterned to leave the resist film 12 on the gate region (as shown in FIG. 1(b)). Thereafter, using the resist film 12 as a mask, the gate electrode material film 41 is selectively removed by reactive ion etching (RIE) or the like to form a gate electrode 42 made of a high melting point metal.

Next, using plasma CVD method or sputtering method,
The tube is covered with an inorganic material x film 21 made of Sin, SIN, etc. (as shown in FIG. 1(c)). Next, a resist film 13 is deposited using a spin code method and patterned using photolithography to cover the inorganic material film 21 on the drain region side of the gate electrode 42. When the inorganic material film 21 is removed by etching or the like using this resist film 13 as a mask, the inorganic material film 21 remains only on the drain region side of the gate electrode 42 (as shown in FIG. 1(d)).

Thereafter, the resist film 13 is removed by immersion in acetone or ashing, and the inorganic material film 21 is removed by RIE or the like. Then, as shown in FIG. 1(e), when the inorganic material film 21 remains only on the side wall of the gate electrode 42 on the drain region side, the above etching is stopped. Next, a resist film 14 is deposited by a spin code method or the like, a MESFET formation region is opened by photolithography, and n-type impurity ions are implanted using the resist film 14, inorganic material film 21, and gate electrode 42 as masks. .

This ion implantation is performed at a high concentration, thereby forming the source region 3 in contact with the gate electrode 42 and the drain region 4 separated from the gate electrode (as shown in FIG. 1(f)).
.

Next, the resist film 14 is removed and annealing is performed at about 800° C. in an As Ha atmosphere to form the ion-implanted layer 2,
Activate 3.4. Thereafter, ohmic electrodes 45 and 46 are formed by a lift-off method, and a MESFET is completed by a self-alignment process (as shown in FIG. 1 (g)).
.

In the MESFET of the above embodiment, the gate electrode 42 and the source region 3 are in contact with each other. To eliminate this,
After the step shown in FIG. 1(f), the inorganic material film 21 is removed by etching, and the gate electrode 42 is etched in the same direction only from the inside.

〔Effect of the invention〕

As explained above in detail, in the present invention, an inorganic material film does not exist on the side wall of the gate electrode on the source region side, but exists on the side wall of the drain region side. Source/drain regions are formed by ion implantation using a mask. Therefore, it is possible to easily realize a MESFET having a gate electrode shifted toward the source region and having a high drain breakdown voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an element according to manufacturing steps, showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Operating layer, 3... Source region, 4... Drain region hA, 11. 12. 13
- Photoresist film, 21... Inorganic material film, 41...
- Gate electrode material film, 42...gate electrode, 45.4
6...Ohmic electrode. Patent Applicant Sumitomo Electric Industries Co., Ltd. Representative Patent Attorney Yoshi Hase
/2) Figure 1 (1) Arch-plants (2/2) Figure 1 (2)

Claims (1)

[Claims] 1. A first step of forming a gate electrode made of a high melting point metal on a semiconductor substrate on which an active layer has been formed in advance; and after depositing an inorganic material film, a drain region side of the gate electrode is formed. a second step of forming a resist pattern covering the inorganic material film and removing the inorganic material film using the resist pattern as a mask; and removing the resist pattern and etching the inorganic material film to remove the gate. a third step of leaving the inorganic material film on the side wall of the electrode on the drain region side; and using the inorganic material film remaining on the gate electrode and its side wall as a mask, impurities are implanted at a high concentration into the semiconductor substrate. and a fourth step of forming source and drain regions. 2. The method for manufacturing a field effect transistor according to claim 1, wherein the etching in the third step is reactive ion etching.