JPS60136263A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain with high yield super high frequency MESFET's having short gate lengths, small source parasitic resistances, and no possibility of the decrease in gate widthstand voltage by including the process of forming a high concentration region in a substrate around a wall metal film and a wall insulation film. CONSTITUTION:After an oxide film 10 is deposited over the entire surface by the sputtering method, the part other than only the upright part of the oxide film 10 is removed by RIE, when a wall oxide film 10a integral with a wall metal film 19a is formed. Next, on removal of a pattern 8 by plasma etching, the films 9a and 10a are left on the substrate. Therefore, when annealing is carried out after impurity ions are implanted to a low concentration region 7 on the substrate by using the films 9a and 10a as a mask, n-type high concentration regions 3 and 4 are formed on the substrate surface around the films 9a and 10a. The regions 3 and 4 serve as the source region and the drain region of a MESFET, respectively; on the other hand, the remaining n-type low concentration region serves as the gate region 2.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for manufacturing a field-effect semiconductor device for ultra-high frequencies such as a GaAs ME'SFET. It relates to a manufacturing method for the device.

[Technical Background of the Invention] Figure 1 shows the cross-sectional structure of the main parts of a junction field effect device for ultra-high frequencies such as a GaAs MESFET, in which 1 is a semi-insulating substrate and 2 is a low-concentration substrate. gate area,
3 is a highly doped source region, 4 is a highly doped drain region,
5 is a gate electrode.

Further, 6 is a surface depletion layer generated during operation of the element,
Rs and Ro are a source parasitic resistance and a drain parasitic resistance occurring between the gate electrode 5 and the source region 3 and drain region 4.

The operating characteristics of the field effect device having the structure described above are influenced by the source parasitic resistance Rr and the drain parasitic resistance R9 generated in the gate region 2, and the non-saturation of the device when Rs and RD are impossible values. The transfer conductance in the region is 1/1+ (Rs + Ro) (proportional to I, and the transfer conductance in the saturated region is 1/1+Rs (]
It is known that it is proportional to s. Here, (),
! ; Is is the transfer conductance in the non-saturated region and the saturated region when Rs and Ro are zero. ) Therefore, in order to form an element with good high frequency characteristics (71-, that is, large transfer conductance), Rs and R
It is necessary to reduce the value of o.
However, the values of Rs and Ro are not shown in FIG. 1, but the values of Is and ID (i.e., the distance between the electrode and the source region I!
Since it is proportional to s and the distance 1o between the gate electrode and the drain region, in order to reduce the values of Rs and Ro, it is necessary to reduce the values of 1s and ID.

In addition to the above requirements, it is also necessary to reduce the gate length 1G in order to form a field effect element with good high frequency characteristics.

On the other hand, if RD is made too small, the gate withstand voltage will drop, so it is not preferable to make RD too small.

Therefore, in order to form a high-frequency field-effect device with a high gate breakdown voltage and high transfer conductance, while Rs is close to zero, it is necessary that Ro be larger than a certain value. Controlling RD has not been possible with conventional device manufacturing methods.

A conventional method of manufacturing a field effect device for ultra-high frequencies will be explained below.

GaAs M used as ultra-high frequency semiconductor elements
There are two methods for manufacturing an ESFET, as shown in FIGS. 2 and 3 of the attached drawings.

The first method is to first
- N-type low concentration region 7 on semi-insulating substrate 1 made of As
After forming the low concentration region 7, impurities are selectively introduced into the low concentration region 7 (for example, by implanting ions using a resist pattern as a mask and then annealing), the source region [3 and drain region 4, which is a high concentration region], and the low concentration region 7 are formed. In this method, a gate region 2 of high concentration is formed, and then a Schottky gate electrode 5 is formed on the gate region 2 by a lift-off method as shown in FIG. 2(1).

On the other hand, in the second method, as shown in Figure 3(a), Ga
After forming an n-type low concentration region 7 on a semi-insulating substrate 1 made of As, an electrode 5 of Schottky goo 1 is formed on the low concentration region 7 as shown in FIG. 3(b). By forming impurities into the substrate around the goo 1 to the electrode using the gate electrode 5 as a mask, a low concentration gate region 2 is formed in both the high concentration source region 3 and the drain region 4. The method is to do so.

[Problems with Background Art] In the first method, since the regions 1 to 5 are formed after the source region 3 and drain region 4 are formed, the source region 3 and drain region 4 must be self-aligned with the gate electrode 5. Therefore, it was inevitable that the values of 1s and j2o would become large. Therefore, the element formed by the first method has a large source parasitic resistance R5, resulting in a small transfer conductance and poor high frequency characteristics. Further, there was also a drawback that the electrodes 1 to 5 were difficult to peel off.

On the other hand, the second method solves the problems of the first method, and according to this method, the source region and the train region are formed in a self-aligned manner using the gate electrode 5 as a mask. Because of the above j! The values of s and 1D will be very small and therefore the values of F<s and Ro will also be small. However, in this second method, during annealing after ion implantation, the implanted ions diffuse laterally and expand to a position where the ends of the drain region 4 and source region 3 contact the gate electrode 5, and as a result, the 1D There have been problems such as the gate breakdown voltage being significantly degraded as the value approaches zero, and the threshold voltage becoming uncontrollable as the 1S value approaches zero. In addition, this method also has the disadvantage that the electrodes 1 to 5 may peel off or be thin.

Therefore, in any of the above methods, the spear and J
Because it was not possible to precisely control the lo value, devices manufactured using conventional methods (characteristics tended to vary easily and yields were poor. Since the gate length 1 was determined by Since a mask must be prepared for each different element, the cost of mask manufacturing tools and the like is quite high, causing an increase in the manufacturing cost of the element.

[Object of the Invention] An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the various problems described above.

[Summary of the Invention] As described in the claims, the method according to the present invention provides (I) perpendicular to the surface of a semi-insulating substrate or a semiconductor substrate on which a region of a specific conductivity type is formed; (n) forming a metal film to serve as an electrode on the entire surface of the substrate;
III) anisotropically etching the metal film to form a vertical wall-like metal film portion covering the side surface of the pattern;
IV) A step of forming an insulating film on the entire surface of the substrate, and (L)
a step of forming a vertical wall-like insulating film part integral with the wall-like metal film part by anisotropically etching the insulating film; (Vl) a step of removing the pattern by selective etching; ) forming a high concentration region in the substrate around the metal film portion and the wall-like insulating film portion after ion implantation into the surface of the substrate using the wall-like metal film portion and the wall-like insulating film portion as a mask; It is characterized in that it includes lν.

According to the method of the present invention, for example, the source region and drain region of a MESFET can be formed in a self-aligned manner using the gate electrode as a mask, and the source region and drain region can be prevented from coming into contact with the gate electrode. Therefore, there is no risk of gate breakdown voltage deterioration, and high-frequency semiconductor devices with large transfer conductance can be produced at a high yield.

[Embodiments of the Invention] Embodiments of the present invention will be described below with reference to FIGS. 4 and 5 of the accompanying drawings. Figures 4(a) to 4
Figure ([) is a cross-sectional view showing the first example in which the method of the present invention is applied to manufacturing a Ga AS MESFET in the order of steps.

In the method of the present invention, first, the GaAS base plate 1 upper plate impurity temperature 3
X 1015/ C1l+” low concentration region 1t (n type) 7
After forming a pattern 8 with a thickness of 1.5 μm, a pattern 8 with vertical sides is formed using a resist b or an oxide film as shown in FIG. 4(a).
Form as shown. The pattern 8 is formed by forming a metal 9, a resist film, an oxide film, etc. on the entire surface of the substrate 1, and then selecting the metal film, resist film, or oxide film by anisotropic etching such as reactive ion etching (RIE). It is formed by etching. In this example, the pattern 8 is 5i3Nal15! with a thickness of 8000X.
was formed.

After forming the pattern 8, a metal film 9 is formed on the entire surface as shown in FIG. 4(a). This metal film 9 is made of a metal that forms a Schottky junction with the Qa AS substrate,
TiW was used in this example. The metal film 9 had a thickness of 3000 mm and was formed by sputtering.

Next, other parts of the metal film 9 except for the parts attached to the side surfaces of the pattern 8 are etched by reactive ion etching (
Then, as shown in FIG. 4(b), a wall-shaped metal film portion 9a is formed which adheres to the side surface of the pattern 8.
This wall-shaped metal film portion 9a constitutes the gate electrode of the MESFET, and its height h is 7000X and the width J, that is, the length l, is 2000X.

Next, as shown in FIG. 4(C), an oxide film 10 having a thickness of 1500× is deposited on the entire surface by sputtering, and only the upright portions of the oxide film 10 are removed by RIE, and the other portions are removed. As shown in Figure (d), the wall-like metal film portion 9a
A wall-like oxide film portion 16a is formed integrally with. The width or length of this wall-like oxide film portion 10a is 1000 mm.

Next, when the pattern 8 is removed by plasma etching C, a wall-like metal film portion 9a and a wall-like oxide film portion 10a are left on the substrate as shown in FIG. 4(e). After ion implantation of an impurity such as Si into the low concentration region 1*7 on the substrate using the wall-like oxide film portion 10a as a mask, annealing is performed at 800° C. for 10 minutes.
As shown in FIG. 4([), for example, an n-type high-temperature film with a thickness of 4 μm and an impurity i9 degree of 3×1016/Cm3 is applied to the substrate surface around the wall-like metal film portion 9a and the wall-like oxide film portion 10a. A concentrated region 3.4 is formed. These high concentration regions 3 and 4 become the source region and drain region of the MESFET, respectively, while the wall-like metal film portion 9a and the wall-like oxide film portion 10
The n-type low m degree region left directly below a becomes the gate region 2. Further, the wall-like metal film portion 9a is the wall-like oxide film portion 1.
The gate electrode 5 is formed integrally with the gate electrode 0a.

In the GaAs MESFET shown in FIG. 4(f), the value of As is close to zero, so the transfer conductance is large, and it has good high frequency characteristics, but on the other hand, the distance An between the drain region 4 and the gate electrode 5 is Since it is sufficiently larger than 15, the gate breakdown voltage is also large. Furthermore, since the gate electrode is formed integrally with the wall-like oxide film portion 10a, the adhesion force to the substrate is large despite the very large aspect ratio (li-plane surface structure horizontal ratio) of the metal portion of the gate electrode. Therefore, peeling of the Ge-1 electrode is less likely to occur.

Furthermore, since the gate length lG (see FIG. 1) is determined by the thickness of the wall-like metal film portion 9a in the method of the present invention, it is possible to realize a very small gate length as desired according to the method of the present invention. M E S F with good high frequency characteristics.
ET is obtained.

FIG. 5 shows a part of the method of the second embodiment of the present invention. The first half of the method of the second embodiment is shown in Figure 4 (a
) to FIG. 4(e), and the remaining latter half steps are shown in FIG. 5(a) to FIG. 5(C).

In the method of the second embodiment of the present invention, FIGS.
After completing the steps up to FIG. 5(e), the second insulating film 11 is formed on the entire surface as shown in FIG. A second wall-like insulating film portion is attached to each side of the wall-like metal film portion 9a and the first wall-like insulating film portion 10a, as shown in FIG. 5(b). 11a is formed. Next, using the gate electrode 5 formed by the wall-like metal film portion 9a and the first and second wall-like insulating film portions 10a and 11a as a mask, impurities such as 81 are injected onto the substrate surface around the electrodes. After ion implantation, annealing is performed at 800° C. for 10 minutes to form a source region 3 and a drain region 4 on both sides of the electrodes 1 to 5.

Finally, when the Ge layer 12 and the AU layer 13 are successively deposited on the source region 3, drain region 4, and gate electrode, these two layers become the source electrode and the drain electrode, respectively, and The two layers deposited on the top surface serve as lead connection pads for the gate electrode.

In the method of the second embodiment, the distance 1s between the gate electrode and the source region is determined by the thickness of the second wall-like insulating film portion 11a in the source region forming step, and the distance between the gate electrode and the drain region is 1o is the first and second wall-shaped insulating film portions 10a and 1 in the train region forming step.
Since it is determined by the total film thickness of 1a, the values of 1s and 1D can be finely controlled, and the values of j2s and io
There is no fear that the value of will become zero or become undesirable. Further, since the wall-shaped metal film portion 9a, which is the gate electrode, is sandwiched between the wall-like insulating film portions 10a and 11a from both sides, there is no risk of the gate electrode collapsing or peeling off from the substrate even if the gate electrode has a large aspect ratio.

[Effects of the Invention] As explained above, according to the method of the present invention, the gate length is shorter than that of conventional MESFETs, the source parasitic resistance is small, and the ultra-high frequency ME'5FETs can be manufactured with high yield. Furthermore, the method of the present invention does not require an optical exposure method when forming the gate electrode, which simplifies the process and does not require a mask manufacturing tool, making it possible to reduce manufacturing costs compared to conventional methods. Further, according to the method of the present invention, since a mask is not required when forming the gate electrode, devices with various gate lengths can be manufactured, and there is no need to manufacture a mask when changing the gate length.

It should be noted that, although the above-mentioned embodiments have been described with respect to a method for manufacturing a Ga As MESFET, it is a matter of course that the method of the present invention can also be applied to a method for manufacturing other types of semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part of a junction field effect device, FIGS. 2 and 3 are diagrams for explaining a conventional manufacturing method,
FIG. 4 is a diagram showing the first embodiment of the method of the present invention in order of steps, and FIG. 5 is a diagram showing the latter half of the second embodiment of the method of the present invention in order of steps. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate region, 3...Source region, 4...Drain region, 5...Gate electrode, 7...Low concentration region, 8...Pattern. Patent applicant Tokyo Shibaura Electric Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A step of forming a predetermined pattern having side surfaces perpendicular to the surface of a semi-insulating substrate or a semiconductor substrate on which a specific conductivity type region is formed, and forming a predetermined pattern on the entire surface of the substrate. a step of forming a metal film on the substrate, a step of anisotropically etching the metal film to form a vertical wall-like metal film portion covering the side surface of the pattern, and a step of forming an insulating film on the entire surface of the substrate. a step of anisotropically etching the insulating film to form a vertical wall-like insulating film portion covering the side surface of the wall-like metal film portion; a step of removing the pattern by selective etching; By implanting ions into the surface of the substrate using the shaped metal film portion and the wall-shaped insulating film portion as masks, a high concentration region is formed on the substrate surface around the wall-shaped metal film portion and the wall-shaped insulating film portion. A method for manufacturing a semiconductor device, including a step of forming the semiconductor device. 2. Forming a predetermined pattern with side surfaces perpendicular to the surface of a semi-insulating or semiconductor substrate on which a specific conductivity type region is formed, and forming a metal film on the entire surface of the substrate. a step of anisotropically etching the metal film to form a vertical wall-like metal film portion covering the side surface of the pattern; a step of forming a first insulating film over the entire surface of the substrate; forming a vertical first wall-like insulating film portion that covers the side surface of the wall-like metal film portion by anisotropically etching the second insulating film; and removing the pattern by selective etching. forming a second insulating film on the wall-like metal film portion, the second wall-like insulating film portion, and the surface of the substrate; and anisotropically etching the second insulating film to remove the wall. forming a vertical second wall-like insulating film portion covering each side of the metal film portion and the second wall-like insulating film portion; forming a high concentration region in the substrate around the upright piece by implanting ions into the substrate around the upright piece using the upright piece consisting of the membrane portion and the second wall-like insulating film portion as a mask; A method for manufacturing a semiconductor device including: