JPH02181519A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To obtain a frequency dividing circuit driven by an applied frequency dividing rate by combining a rate multiplexer and an N-frequency dividing counter to constitute the circuit and controlling the N-frequency dividing counter by the output of the rate multiplexer. CONSTITUTION:The frequency dividing circuit is provided with a 1st frequency dividing circuit A controlled by the decimal part J of a frequency dividing rate input and constituted of a rate multiplexer having an integer frequency dividing rate K<a>/N, the 2nd frequency dividing circuit B controlled by the integer part I of the frequency dividing rate input and constituted of an M frequency dividing counter having an integer frequency dividing rate M and a frequency dividing output terminal connected to the output of the circuit B. Provided that K and (a) are natural numbers >=2 and N is an integer. A pulse input terminal is connected to the pulse input CL of the circuit B and the frequency dividing output of the circuit B is connected to the pulse input CL of the circuit A. The frequency dividing period of the circuit B is increased/decreased in accordance with the frequency dividing output of the circuit A. Thus, a frequency dividing rate based upon a real number can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frequency divider circuit whose frequency division ratio can be controlled by an external signal.

(Prior Art) A conventional frequency divider circuit is divided into a rate multiplexer and a divide-by-N counter. An example circuit of a binary rate multiplexer is shown in FIG. 4, and an example of its operation is shown in FIG. In the figure, the part 1-1 consists of four T-FFs and constitutes a binary counter that counts up by pulse manual ACL.
sQ-QIQo becomes the value of the binary counter. When the output of the counter and the inverted output are input to the AND-OR circuit 1-2, the output of the AND-OR circuit (divided output A. N.

In response to this, an output as shown in FIG. 5 is obtained. This output signal has pulses generated as many times as the frequency division ratio control manual power N within one period (24 pulses) of the binary counter, and this
The frequency division ratio of the forward rate multiplexer is 247N.

An example of the circuit of the N frequency division counter is shown in FIG. 6, and an example of its operation is shown in FIG. In the figure, the part 3-2 consists of four D-FFs.
It constitutes a base/subtraction counter, QaQzQl·Qo becomes the value of the binary counter, and the initial value of the counter can be loaded by the circuit 3-3. The output of this binary subtraction counter is input to a 3-1 AND circuit, and "1" is output from the AND circuit only when the value of the binary counter is "1". "l" from the AND circuit of 3-1
When " is output, the AND gate 3-0 is opened, a pulse is output to the frequency division output, and at the same time, the frequency division ratio N"N5NJ+No is loaded into the binary counter by the circuit 3-3. As a result of the above, the value of the binary subtraction counter changes to N, N-1, . . . 2 every time a pulse is input, as shown in Figure 7.
．． 1. N, N-1, the value of the counter becomes "l" every time N pulses are input, and one pulse is output to the frequency divided output. Since one output pulse is output for every N pulses, the frequency division ratio of this N frequency division counter is N.

The division ratio of the rate multiplexer is 21/N or to”
/N, and in order to input a small number of division ratios, arithmetic processing is required.Even if arithmetic processing is performed, it is inevitable that errors will occur, especially when the division ratio is large. The error will be large.

The frequency division ratio of the N frequency division counter is N, and frequency division with a frequency division ratio that has a decimal part cannot be performed as it is, so the input pulse frequency is increased and the frequency division ratio is relatively converted to an integer. Although it is necessary, it is often not easy to easily obtain a high frequency signal synchronized with the input pulse because it requires a complicated circuit such as a PLL.

(Problems to be Solved by the Invention) An object of the present invention is to provide a frequency divider circuit that operates at a given frequency division ratio even when the frequency division ratio in the frequency divider circuit is given by a small number. .

(Means for Solving the Problems) A feature of the present invention for achieving the above object is that the present invention has a frequency division ratio input terminal and a pulse input terminal, and an external signal applied to the frequency division ratio input terminal allows the pulse input terminal to be input to the frequency division ratio input terminal. In a frequency divider circuit where the frequency division ratio of the number of input pulses is controlled, the frequency division ratio of the integer ratio - (K is a natural number of 2 or more, a
is a natural number greater than or equal to 2, and N is an integer), and the first frequency divider circuit (A) is a rate multiplexer, and the M circuit is controlled by the integer part (I) of the frequency division ratio input and has an integer frequency division ratio (M). It has a second frequency division circuit (B) using a frequency division counter, and a frequency division output terminal connected to the output of the second frequency division circuit (B),
The pulse input terminal is connected to the pulse input (CL) of the second frequency divider circuit (B), and the frequency division output of the second frequency divider circuit (B) is connected to the pulse input of the first frequency divider circuit (A). (CL), and realizes a frequency division ratio based on a real number by increasing or decreasing the frequency division period of the second frequency division circuit (B) using the frequency division output of the first frequency division circuit (A). It's in the circuit.

(Function) As shown in FIG. 1, the present invention provides a rate multiplexer (
It has a structure that combines A) and an N-divided counter (B), and the output of the N-divided counter is connected to the input of a rate multiplexer, and the N-divided counter is controlled by the output of the rate multiplexer. By changing the frequency division period by, for example, 1, it is attempted to obtain output pulses having a small number of frequency division ratios on average. Conventionally, for such applications, an input pulse is multiplied by a PLL, etc., and a pulse is generated such that the desired frequency division ratio multiplied by the multiplication rate is an integer. A circuit that divides the frequency using a frequency circuit was required.

(Example) The operation of the frequency dividing circuit according to the present invention will be described below with reference to the drawings. Here, the pulse input 102 is frequency-divided and the frequency-divided output 1
04.

FIG. 1 shows a block diagram of the present invention. Division ratio input 100
is divided into an integer part and a decimal part J, the decimal part J is input to a rate multiplexer A, and the integer part is input to a divide-by-N counter B. The frequency division output of rate multiplexer A is not gated by the input pulse, but is controlled manually by N division counter B.
Input to NT.

The N frequency division counter B has control inputs as shown in FIG. As shown in Fig. 9, the operation of the N frequency division counter B is such that when the control input is L°, the counter value expressed in binary numbers as the output value 03Q-QlQo of each flip-flop is N.
The change from 1 to 1 is repeated, and as a result, N frequency division operation is performed. When the control input is H°, the counter value changes from N to 0, so the frequency increases by N+1+1. As a result, the frequency division ratio can be increased or decreased by 1 depending on the control input.

In addition, in Figure 9, 1 is the pulse person corner of Figure 8.

Clock pulses before frequency division input from 2 and 5 are the 8th
The outputs Q, Q, Q, and Qo of the D flip-flop in the figure are expressed in binary numbers, and 3 and 6 are the frequency-divided outputs B in FIG. Outputs 4 and 7 from Ua are control human power BCN in Figure 8.
The division ratio control input is input from T. 2 to 4 show operation examples when the control input is D when the counter value is 1, and 5 to 7 are the control input when the counter value is 1. An example of operation in case of O is shown below.

Set the division ratio to 3.4 (hexadecimal) (I=3. J=4)
FIG. 2 shows an example of the operation in the case of this.

In Figure 2, 2-1 and 2-6 are the clock pulses before frequency division input from the pulse input in Figure 1, and 2-2 is the D flip-flop in the N frequency division counter B in Figure 1. output 2
The numerical values 2-3 and 2-7 expressed in base numbers are the outputs of this frequency dividing circuit output from the N frequency dividing counter B in Fig. 1, 2-4
and 2-8 are numerical values representing the output of the D flip-flop in the rate multiplexer in Fig. 1 in binary, and 2-5 and 2
-9 is the output from the rate multiplexer A in FIG. 2-1 to 2-5 indicate the operation during the period when the A counter value is from 0 to 2, and 2-6 to 2-10 indicate the operation during the entire cycle of the A counter.

Output pulse (2-3
, 2-7) is output once, the rate multiplexer counts up (2-4.2-8), so 16 output pulses constitute one cycle (2-12). The output of the rate multiplexer (2-9) is high only four times in one cycle.

becomes. When the output of rate multiplexer A (2-5, 2-9) is °L°, N-divider counter B operates at a division ratio of 3 (2-10), and when the output (2-10) of rate multiplexer A is °H°, it operates at a division ratio of 4. (2-11) Therefore, during one cycle of rate multiplexer A, N frequency division counter B performs 3 frequency division operation 12 times and 4 frequency division operation 4 times, and the number of input pulses during this period is (
3X 12+ (3+ l) X 4) = 52. On the other hand, since the total number of output pulses is 16, therefore,
The frequency division ratio (number of input pulses: number of output pulses) is 52/16 =
It becomes 3+4/16.

If a similar calculation is performed for any input of the integer part of the human power I>O11 and the matching number of the human power J, the output of the rate multiplexer becomes °H' only 5 times during one period of 16 output pulses. The N frequency division counter operates with the frequency division ratio when the output of the rate multiplexer is °L, and when the output of the rate multiplexer is °H, it operates with the frequency division ratio (I+1
), during one period of the rate multiplexer, the N frequency division counter performs (16-J) times of frequency division operations, and (I
+1) Frequency division operation will be performed 5 times, and the number of input pulses during this time will be (IX (16-J) + (I + 1) x J))
= Ix16+J, therefore, the frequency division ratio (number of manual pulses: number of output pulses) is (Ix 16+J)/16=I+J
/16, which matches the input value.

FIG. 3 shows an example of a device using this frequency dividing circuit.

The output of the oscillator is directly input to the stepping motor My, and a signal is input to the stepping motor Mx through a frequency dividing circuit. My moves the table in the Y direction, and Mx moves the table in the X direction. If the direction in which the table moves is θ as shown in the figure, the value of tan θ can be directly input as the frequency division ratio input to the frequency divider circuit. Conventionally, for such applications, it was necessary to attach a frequency divider circuit to the input of My, and to calculate the frequency division ratio of the frequency divider circuit so that the two stepping motors could operate at the correct speed.

In addition, when this circuit is used in the frequency divider circuit of a PLL (phase lock circuit), it is possible to completely change the configuration of other parts (without changing the PLL circuit).
The oscillation frequency step can be made fine.

In this example, the division ratio input was explained using hexadecimal numbers, but it is exactly the same even if it is replaced with binary numbers.Also, if a decimal counter is used for the rate multiplexer and N division counter, input in decimal numbers is also possible. be.

(Effects of the Invention) As explained above, the frequency divider circuit according to the present invention allows the frequency division ratio to be input as a decimal number.
A frequency divider circuit can be directly incorporated into applications that require combinations of LLs.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment that best represents the features of the present invention, Fig. 2 is an example of the operation of the embodiment, Fig. 3 is an example of a device using this frequency dividing circuit, and Fig. 4 is a conventional A circuit example of a rate multiplexer, FIG. 5 is an example of the operation of a rate multiplexer, FIG. 6 is an example of a circuit of a conventional divide-by-N counter, FIG. 7 is an example of the operation of a divide-by-N counter, and FIG. 8 is a configuration of the present invention. FIG. 9 is an example of a circuit of an N frequency division counter whose frequency division ratio can be changed by 1 by control input. FIG. 9 is an example of the operation of the circuit shown in FIG. 8. (Symbols in Figure 1) Rate multiplexer, N frequency division counter, decimal part, integer part, ; Division ratio input; Pulse input; Division output

Claims (1)

[Claims of Claims] A frequency dividing circuit that has a frequency division ratio input terminal and a pulse input terminal, and the frequency division ratio of the number of pulses input to the pulse input terminal is controlled by an external signal applied to the frequency division ratio input terminal. is controlled by the decimal part (J) of the division ratio input and has an integer division ratio K_a/N (K is a natural number greater than or equal to 2, a is a natural number greater than or equal to 2, and N is an integer). 1 frequency divider circuit (A), and a second frequency divider circuit (B
), and a frequency division output terminal connected to the output of the second frequency division circuit (B), and the pulse input terminal is connected to the pulse input (CL) of the second frequency division circuit (B). , the frequency division output of the second frequency division circuit (B) is connected to the pulse input (CL) of the first frequency division circuit (A), and the frequency division output of the first frequency division circuit (A) A frequency divider circuit characterized in that a frequency division ratio based on a real number is realized by increasing or decreasing the frequency division period of the frequency divider circuit (B).