JPH02182009A - Buffer amplifier circuit - Google Patents

Abstract

PURPOSE:To make a junction capacitance equivalently zero, to reduce harmonic wave distortion considerably and to improve the signal band width by providing a 2nd follower circuit so as to supply a compensation voltage with the same amplitude and phase as a voltage changed at an input terminal of a 1st follower circuit to a collector or a drain terminal of the 1st follower circuit. CONSTITUTION:A voltage change in an input terminal 10 of a parallel A/D converter 10 is detected by an emitter follower circuit comprising a transistor(TR) 2, the voltage is converted into a current across a resistor 8, the current is supplied to a resistor 8 via a TR 3, in which current voltage conversion is applied and a compensation voltage is generated and fed to a collector terminal 11 of an emitter follower circuit being a component of a parallel A/D converter via a TR 4 in-phase. In this case, the resistance of the resistors 6, 8 is selected equal to make the voltage change at a base terminal of the emitter follower circuit of an input section of the parallel A/D converter 18, that is, the voltage change at the input terminal 10 and the collector terminal 11 equal is each other, and the base-collector junction capacitance is made equivalently zero. Moreover, the collector terminal of a TR 1 is connected to the collector terminal 11 for the same purpose.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a buffer amplifier circuit with low distortion and high operating speed.

(Prior art) In the case of a conventional follower circuit, when a large amplitude voltage is applied to the input terminal, harmonics are generated due to the voltage dependence of the base-collector (or gate-drain) junction capacitance value. There is a problem that distortion is generated and the signal band is limited by the capacitance value.

This problem occurs in technical fields where the harmonic distortion generated in the follower circuit affects the performance of the entire circuit, that is, parallel type A/D converters in which a large number of follower circuits are connected in parallel to the input terminal. This was especially noticeable in sample-and-hold circuits mainly composed of follower circuits.

FIG. 14 shows a conventional N-bit parallel A/D converter. In this figure, 10 is a parallel A/D converter input terminal, 11 is a node, 12 to 1'4 are transistors, 15 to 17 are constant current sources, 36 is a voltage source, and 37 is an input terminal.In this case, the input terminal 10 and 2N emitter follower circuits are connected in parallel.

FIG. 15 shows a second conventional circuit used as an output buffer amplifier of a sample and hold circuit. In this figure, 100 is an input terminal, 102 to 107 are transistors, 108 is a voltage source, 109 is a current source, and 124 and 125 are nodes.

FIG. 16 shows a third conventional circuit used as an output buffer amplifier of a sample and hold circuit. In this figure, 5o is an input terminal, 51.52 is a transistor, 53
．． 54 is a current source, 55 is a voltage source, and 56 is an output terminal.

[Problem to be solved by the invention]

In the conventional circuit shown in FIG. 14 above, the base-collector junction capacitance value at the input terminal 10 is a very large value, and this causes harmonic distortion and signal band deterioration in the parallel A/D converter. This is one of the main causes of deterioration of dynamic accuracy during high-speed operation. In order to drive the large human power capacity of this parallel A/D converter, the first
An emitter follower circuit composed of a transistor 38 and a current source 39 shown in FIG. 4 has been used. However, in this case as well, in order to reduce the harmonic distortion at the terminal 1o, it is necessary to make the current value of the transistor 3 very large, and accordingly, the size of the transistor 38, that is, the junction capacitance increases. There was a problem in that it introduced a new distortion deterioration factor.

In addition, in the conventional circuit shown in FIG. 15, a signal with a large amplitude of about 2Vpp is manually applied to the input terminal 1o○ during sampling, so as in the case of the conventional circuit shown in FIG.
There is a problem in that the voltage dependence of the base-collector junction capacitance values of the transistors 102 and 105 generates harmonic distortion and limits the signal band.

Further, the conventional circuit shown in FIG. 16 is a third conventional circuit used as an output buffer amplifier of a sample-and-hold circuit. In this circuit, since a signal with a large amplitude is input to the input terminal 5o during sampling, the voltage dependence of the base-collector junction capacitance of the transistors 51 and 52 is There are problems in that it generates harmonic distortion and limits the signal band.

An object of the present invention is to reduce the junction capacitance value to equivalently zero, thereby significantly reducing harmonic distortion caused by the voltage dependence of the junction capacitance value and improving the signal band.

[Means to solve the problem]

The buffer amplifier circuit according to the present invention includes a buffer amplifier circuit connected to an input terminal or an output terminal of the first follower circuit for generating a compensation voltage having the same amplitude and phase as a voltage change at the input terminal of the first follower circuit. 2 follower circuits, and means for supplying a compensation voltage to the collector or drain terminal of the first follower circuit.

In addition, in a transistor or diode formed in an n-well or p-well separated from an IC substrate, a follower circuit detects a potential change in a region other than the rc substrate adjacent to the n-well or p-well. It has means for applying changes to the n-well or p-well.

[Effect]

In this invention, the second follower circuit generates a compensation voltage having the same amplitude and phase as the voltage change at the input terminal of the first follower circuit, and this compensation voltage is applied to the collector or drain terminal of the first follower circuit. The base-collector or gate-train bias voltage is kept constant, and the junction capacitance value is made equivalent to zero.

In addition, by detecting potential changes in areas other than the IC substrate adjacent to the n-well or p-well using a follower circuit, and supplying the potential changes to the n-well or p-well, the junction capacitance value can be equivalently reduced to zero. do.

〔Example〕

Figure 1 shows the conventional parallel N-bit A/D shown in Figure 14.
This is a first embodiment in which the present invention is applied to a converter. In this figure, 1 to 4 are transistors, 5 is a current source, 6 to 8 are resistors, 20 is an input terminal, 21 is a node, and 22.23 is a voltage source. A voltage change at the input terminal 10 of the parallel A/D converter 18 is detected by an emitter follower circuit consisting of a transistor 2, converted into voltage and current by a resistor 6, and this current is supplied to a resistor 8 via a transistor 3. The resistor 8 performs current-voltage conversion to generate a compensation voltage, which is supplied in phase to the collector terminal 11 of an emitter follower circuit constituting a parallel A/D converter via the transistor 4. At this time, by setting the values of the resistors 6 and 8 to be equal, the voltage changes at the base terminal, that is, the input terminal 1o and the collector terminal 11 of the emitter follower circuit at the input section of the parallel A/D converter 18 are made equal. , the base-collector junction capacitance value can be equivalently reduced to zero. Further, for the same purpose, the collector terminal of the transistor 1 is also connected to the collector terminal 11. By applying the present invention to a conventional 8-bit A/DI converter, harmonic distortion at the input terminal 10 can be reduced at an input signal frequency of 200 MHz, compared to the conventional technology using an emitter follower circuit of the transistor 38 shown in FIG. , it was confirmed through circuit simulation that it could be reduced to about 1/25th or less.

FIG. 2 shows a second embodiment of the present invention, in which a conventional parallel type A/
This is an example in which the present invention is applied to a D converter. As in the first embodiment, the voltage change at the input terminal 10 of the parallel A/D converter 18 is detected by the transistor 2, and after voltage-current conversion is performed,
A current/voltage conversion is performed by a resistor 8 through a current mirror circuit including transistors 44 and 45 and resistors 42 and 43 and a transistor 47 to generate a compensation voltage. At this time, the values of resistors 41, 42, 43°46.48 and 8 are set to R411R42+R43, R461, respectively.
R411 and R8 are R42・R4a・Ra −
(R41+R42) By setting the resistance value of the resistor 8 so that it becomes R4s and R4a, it is possible to generate a compensation voltage whose amplitude and phase are equal to those of the input terminal.

FIG. 3 shows a third embodiment of the present invention, which is an example in which the present invention is applied to the conventional parallel type A/D converter 18 shown in FIG. The voltage change at the input terminal 10 of the parallel type A/D converter during one day is detected by an emitter follower circuit composed of a PNP type transistor 23, level shifted by the diodes 24 and 25, and the voltage change at the input terminal 10 of the parallel type A/D converter is detected via the transistor 4. Collector terminal 11 of the emitter follower circuit that constitutes the D converter 18
are supplied in phase. Furthermore, for the same purpose, the same voltage is also supplied to the collector terminal of transistor 1.

FIG. 4 shows a fourth embodiment of the present invention, in which the third embodiment shown in FIG.
An example in which the present invention is further applied to reduce harmonic distortion newly generated due to the voltage dependence of the base-collector junction capacitance of the transistor 23 for the emitter follower circuit for generating a compensation voltage in the embodiment. It is.

In the same figure, a voltage change at the base of the transistor 23 is detected by the transistor 29, and the voltage change at the collector terminal 34 of the transistor 23 is detected via the diode 30 and the transistor 31.
are supplied in phase.

FIG. 5 shows a fifth embodiment of the present invention, in which the third embodiment shown in FIG.
In this embodiment, in order to reduce harmonic distortion newly generated due to the voltage dependence of the base-collector junction capacitance of the transistor 23 for the emitter follower circuit for generating the compensation voltage, a parallel A/D converter is used. 18 input terminals 1
0 and the base terminal of transistor 23, transistors 23, 35 . This is an example using an emitter follower circuit consisting of a resistor 36.

FIG. 6 shows a sixth embodiment of the invention. In the first embodiment shown in FIG.
The transistor 4 for supplying a compensation voltage to the collector terminal of each of the transistors 12 to 14 constituting the transistor is divided into the number of emitter followers (2N pieces), and the transistors 300 to
02, one is distributed to each emitter follower. Note that 303 is a terminal, and 304 is a voltage source. The purpose of this is that in the pattern layout of the parallel A/D conversion LSI, the current flowing through the collector terminals of the transistors 12 to 14 is equal to the current flowing through the base terminals by hr-(
Since the current amplification factor of each transistor is twice as large, the width of the wiring pattern is also wide, and the parasitic capacitance of the pattern is large, which may cause ringing. The aim is to solve this problem by doing so. As in the prior art, inserting a base resistor in each transistor is effective in reducing ringing.

FIG. 7 shows a seventh embodiment of the present invention, in which a transistor 305 is further added for driving the terminal 303 in FIG. The same techniques as in FIGS. 6 and 7 can be applied to the other embodiments shown in FIGS. 2 to 5.

FIG. 8 shows an eighth embodiment of the invention.
This is an example in which the present invention is applied to the conventional circuit shown in FIG. The voltage change at the input terminal 100 is transmitted to the emitter follower circuit 102,
108 and the terminal 11 through the transistor 114.
5.

Potential difference between terminal 115 and terminal 124 and terminal 115 and 1
Since the potential difference between transistors 102 and 105 is always constant, this configuration always keeps the base-collector voltage value of transistors 102 and 105 constant, so the junction capacitance between these bases and collectors becomes equivalently zero, and harmonics It is possible to reduce distortion and improve the input band. Furthermore, since the bias voltages of the transistors 102 to 105 are always kept constant, it is also possible to reduce the bias dependence of droop.

FIG. 9 shows the ninth embodiment of this invention, and the fifteenth embodiment shows the ninth embodiment of the present invention.
This is an example in which the present invention is applied to the conventional circuit shown in the figure. This circuit is an embodiment in which the present invention is applied to reduce harmonic distortion generated by the base-collector junction capacitance of the transistor 108 in the eighth embodiment shown in FIG. The base potential of the transistor 108 is detected by an emitter follower circuit 119 and supplied to the collector terminal 122 of the transistor 108 via the transistor 121.

FIG. 10 shows a tenth embodiment of the present invention, which is an example in which the present invention is applied to the conventional circuit shown in FIG.

Voltage changes at input terminal 50 are detected by emitter follower circuits 57 and 63, respectively, and supplied to collector terminal 61 of transistor 51 and collector terminal 67 of transistor 52 via transistors 60 and 66. Furthermore, since the bias voltages of the transistors 51 and 52 are always kept constant, it is also possible to reduce the bias dependence of droop.

FIG. 11 shows an eleventh embodiment of the present invention, which is an example in which the present invention is applied to equivalently eliminate the base-collector junction capacitance of transistors 57 and 63 shown in FIG. be. The collector terminals of transistor 57 and transistor 63 are connected to terminals 67 and 61, respectively.
This is achieved by connecting to.

FIG. 12 shows a twelfth embodiment of the present invention, which is an example in which the present invention is applied to a conventional sample-and-hold circuit using a diode bridge as a switch.

Since an analog signal with a large amplitude of about 2 Vpp is input to the input terminal 150, harmonic distortion is generated due to the voltage dependence of the collector-substrate capacitance value of the PNP transistor used as a diode bridge. The voltage value of the output terminal 158, which has the same potential as the input terminal 150, is transferred to the buffer amplifier 160.
It has an n-well structure via the transistors 162 and 165, that is, an n-well is created in a p-type substrate, and in this n-well, a collector consisting of a p layer, an n layer, a collector consisting of a p layer, a base, and an emitter are formed. PNP type transistor 151
By supplying it to each of the n-wells of 156 to 156, it is possible to keep the potential difference between the n-well and each terminal of the transistor constant at all times and reduce the harmonic distortion. This n
- The capacitance value between the well and the p-substrate of the IC chip also has voltage dependence, but since this capacitance is driven by the transistor 165 and is not included in the main signal bus,
It has almost no effect on distortion characteristics. Although the case where a PNP transistor having an n-well is used as a bridge has been described above, the present invention can be similarly applied to an NPN transistor having a p-well or a diode formed in a well. In addition, 157 is an n-well, 163 and 164 are diodes, and 166.1
68, 169, 171 are current sources, 167 is a voltage source, 17
0 is a switch.

FIG. 13 shows a thirteenth embodiment of the present invention.
- PNP with a well) - Reduces harmonic distortion caused by junction capacitance between the collector of the PNP transistor and the N-well substrate and deterioration of the frequency band in a conventional differential amplifier mainly composed of transistors. This is an embodiment to which the present invention is applied. As shown in the figure, the collector voltages of transistors 208 and 209 are detected by transistors 212 and 213, respectively, and are supplied to respective n-well terminals 204 and 205. The junction capacitance between the n-well substrate of each transistor and the p-substrate of the IC chip is driven by an emitter follower circuit comprised of transistors 212 and 213.

〔Effect of the invention〕

As described above, the present invention provides a compensation voltage connected to the input terminal or output terminal of the first follower circuit for generating a compensation voltage having the same amplitude and phase as the voltage change at the input terminal of the first follower circuit. 2 follower circuits and means for supplying a compensation voltage to the collector or drain terminal of the first follower circuit, and is formed in an n-well or p-well separated from the IC substrate. In a transistor or diode, a p-layer or nF layer other than the IC substrate adjacent to the n-well or p-well
A follower circuit connected to the p layer or n layer for generating a compensation voltage with the same amplitude and phase as the potential change of J, and means for supplying the compensation voltage to the n-well or p-well. By applying the present invention to a conventional buffer amplifier circuit configured using an emitter follower or source follower circuit, there is an advantage that harmonic distortion and signal band can be significantly improved.

[Brief explanation of the drawing]

1 to 13 are circuit diagrams showing first to third embodiments of the present invention, and FIGS. 14 to 16 are circuit diagrams showing examples of conventional buffer circuits, respectively. In the figure, 1-4.12-14 are transistors, 5.15-
17 is a constant current source, 7.8 is a resistor, 10 is an input terminal, 11
is a collector terminal, 18 is a parallel type A/D converter, 20 is an input terminal, 21 is a terminal, 22.23 is a voltage source, 150 is an input terminal, 151 to 156, 162, 165 are transistors, 163 to 164 are diodes ,166.168,1
69.171 is a current source, and 167 is a voltage source. 166, le) ro, 10 te, 111 den 1 167
Denmaro Diagram Diagram

Claims (2)

[Claims] (1) A second circuit connected to the input terminal or output terminal of the first follower circuit for generating a compensation voltage having the same amplitude and phase as the voltage change at the input terminal of the first follower circuit.
A buffer amplifier circuit comprising: a follower circuit; and means for supplying the compensation voltage to a collector or drain terminal of the first follower circuit. (2) In a transistor or diode formed in an n-well or p-well separated from an IC substrate, it is the same as the potential change of the p layer or n layer other than the IC substrate adjacent to the n-well or p-well. A buffer amplifier circuit comprising a follower circuit connected to the p-layer or n-layer for generating compensation voltages having equal amplitude and phase, and means for supplying the compensation voltage to the n-well or p-well.