JPH02182019A - Delay circuit with unchangeable duty cycle - Google Patents

Abstract

PURPOSE:To obtain a delay circuit whose duty cycle is unchangeable with respect to an input signal and whose delay time is variable by inputting the input signal and a multiplied signal delayed by a 2nd delay circuit and sending the delay signal with the same duty cycle as that of the input signal from the frequency division circuit. CONSTITUTION:When an input signal (1) whose duty cycle is 50% is inputted to a 1st delay circuit 1, a CR charge/discharge waveform (2) is formed by a CR charge/discharge circuit comprising R1,C1 of the delay circuit 1. A transmission signal (6) from a 2nd delay circuit 3 and the input signal (1) are inputted to a frequency divider circuit 4, a frequency signal doubled by a multiplier circuit 2 is frequency-divided into 1/2 to restore the frequency into the original input signal frequency. Since the leading and the trailing are synchronously with the leading of the transmission signal (6) respectively, a synchronizing signal retarded by a delay time (t) from the input signal (1) is sent. That is, the output signal with the same frequency and duty cycle as those of the input signal is obtained.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to create a variable delay circuit with an unchanged duty and a delay time for device testing or a delay circuit with a large delay time. a delay circuit; a frequency multiplier circuit that includes the first delay circuit and doubles the frequency of the human input signal; a second delay circuit having a CR configuration that can change the delay time of the multiplied signal; It consists of a frequency dividing circuit which halves the frequency of the delayed multiplied signal and returns it to the original frequency.The input signal and the delayed multiplied signal are input to the frequency dividing circuit, and the rising edge of the input signal is The frequency dividing circuit is configured to send out a delayed signal synchronized with the falling edge of the signal.

[Industrial application field]

The present invention relates to a delay circuit that outputs an output signal whose duty is not different from that of an input signal and whose delay time is variable.

A delay circuit that is generally used for device testing or for circuits that require a very large delay is used in the test circuit shown in the block diagram of FIG. In the figure, 10 is a pattern generator, 20 is a device under test, and 30 is a delay circuit.

The pattern generator 10 is a signal pattern generator,
Send a data signal and a clock signal to the device under test 20 to test the phase difference, and check to what extent the input phase must be shifted to reach the allowable range on the output side, that is, the operating range of the device under test 20. A delay circuit 30 is inserted into the clock signal sending circuit for testing. This delay circuit 3
0 requires that the delay time be made variable over a wide range.

[Conventional technology]

FIG. 5 shows a conventional delay circuit using the time constant of CR. In the figure, 11 is a variable resistor R12 is a capacitor C
113 and 14 indicate buffer B.

The operation timing chart of this delay circuit is shown in the sixth section.
As shown in the figure. In the figure, ■'' indicates the input signal, ■'' indicates the output waveform of the CR circuit, and ■'' indicates the output signal of the buffer B14.

The circuit operation of a conventional general delay circuit will be explained with reference to FIGS. 5 and 6. The input signal "■" is a clock signal having a phase ratio (duty) of 50%.

This input signal ■° has an output waveform due to charging and discharging of the CR circuit.
° is sent out, detected by the threshold values "H" and "L" at the rising and falling edges of the output waveform, and the output signal {circle around (1)} is sent out through the buffer 14. However, due to the difference in delay time between rising and falling, the phase ratio between the input signal ■' and the output signal ■° differs. Although the delay time can be adjusted using the variable resistor R11, it is difficult to adjust the phase distortion using only this circuit.

[Problem to be solved by the invention]

In the conventional delay circuit using OCR, the phase ratio, that is, the duty, changes, so it cannot be used in areas where precision of the duty is required, such as for device testing. There is also a method of using a delay element, but it is not possible to obtain a large amount of delay with a delay element.

It is an object of the circuit of the present invention to solve these problems and to provide a variable delay circuit for device testing that has no difference in duty from a human input signal.

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, ■ is a first delay circuit with a CR configuration, 2 is a frequency multiplier circuit including the first delay circuit, and 3 is a second delay circuit with a CR configuration that can change the delay time of the multiplied signal. , 4 represents a frequency divider circuit that returns the delayed multiplied signal to its original frequency.

The input signal and the multiplied signal delayed by the second delay circuit 3 are input to a frequency divider circuit 4, and the frequency divider circuit 4 outputs a delayed signal having the same duty as the input signal. do.

[Effect]

When an input signal is input to the first delay circuit 1 having a CR configuration, the output signal whose duty is more distorted than the input signal is converted by the frequency multiplier 2 into a frequency twice as high as that of the input signal. The rising edge of the output waveform of this multiplied frequency is synchronized with the rising edge and falling edge of the input signal, respectively, but the falling edge is synchronized with the rising edge and falling edge of the output signal of the first delay circuit l, so the multiplied frequency is The output waveform of the input frequency is a signal with a duty different from that of the input signal. The output signal of the multiplied frequency with a different duty is inputted to the second delay circuit 3, and the rise of the multiplied signal can be delayed by the variable delay time circuit. Since the rising edge of this delayed signal is synchronized with the rising edge and falling edge of the input signal, the frequency dividing circuit 4
By returning the frequency to 1/2, it is possible to send out an output signal with the same frequency and duty, which is synchronized with the rising and falling edges of the input signal, with the delay time suitably variable.

〔Example〕 A circuit configuration diagram of an embodiment of the present invention is shown in FIG.

In the figure, 1 is a first delay circuit consisting of a resistor R1, a capacitor c1, and a buffer B1, 2 is a multiplier circuit consisting of the first delay circuit and an EXOR circuit EX, and 3 is a variable resistor R.
2, a second delay circuit consisting of a capacitor c2 and a buffer B2; 4, an AND circuit A1 and A2 and a flip-flop F;
A frequency dividing circuit consisting of F is shown.

FIG. 3 shows an operation timing chart of the above embodiment.

In the figure, ■ is the input signal, and ■ is the C of the first delay circuit 1.
RR discharge waveform, ■ is the output signal of the first delay circuit 1, ■ is the output signal of the EX circuit of the multiplier circuit 2, ■ is the CRR discharge waveform of the second delay circuit 3, ■ is the output signal of the second delay circuit 3 The output signal (■) indicates the output signal of the FF circuit of the frequency dividing circuit 4.

The circuit operation of the embodiment will be explained with reference to the circuit configuration diagram in FIG. 2 and the timing chart in FIG. 3.

When the input signal (2) with a duty of 50% is input to the first delay circuit 1, a CR charging/discharging wave trace is formed by the CRR discharge circuit consisting of R1 and CI of the delay circuit 1. Threshold values “+1” and “at the rise and fall of this waveform
By detecting #, an output signal ■ is obtained. Since this output signal ■ has different rising and falling times, it is a delayed signal ■ with a different duty from the input signal ■ as in the past.
is sent. When the EX circuit calculates the exclusive OR of this output signal ■ and the input signal ■, a multiplied signal ■ with twice the frequency whose rise is synchronized with the rise and fall of the input signal, respectively, is output from the EX circuit of the multiplier circuit 2. Sent out. However, the falling edge of the multiplied signal ■ corresponds to the first output signal ■.
Since the output signals are synchronized with the rising and falling edges of , output signals ■ with different delay times and different duties are sent out. When this output signal (■) is delayed by the CRR constant of the second delay circuit 3, a CR charging/discharging waveform (■) is sent out, which is converted into an output signal (■) by detecting the rising and falling thresholds of "11" and "B". This output signal ■ is obtained from the multiplier circuit 2.
This is a signal delayed from the output signal (2) by the CRR constant of C2 and R2. Therefore, the rise of output signal ■ is delayed by the delay time from the rise of output signal ■, but
It is sent out in synchronization with the rising and falling edges of the input signal ■. The output signal ■ and the input signal ■ of this second delay circuit 3
is input to the frequency divider circuit 4, and the frequency signal doubled by the multiplier circuit 2 is divided into 1/2 to return it to the frequency of the original input signal. This output signal ■ is the input signal ■ and the sending signal ■
It is sent out from the FF circuit by the combination of AND circuits A1 and A2, but since the rising and falling edges are respectively synchronized with the rising edge of the sending signal ■, a synchronous signal delayed by the delay time from the input signal ■ is sent out. can do. That is, an output signal having the same frequency and duty as the input signal can be obtained. Further, the delay time can be adjusted as appropriate using the variable resistor R2 of the second delay circuit 3.

In this case, it is possible to perform the test with the same delay time even in crossif using both rising and falling signals.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit block diagram of an embodiment, Fig. 3 is an operation timing chart of the embodiment, and Fig. 4 is a diagram of the principle of the present invention.
The figure shows a block configuration diagram of a test circuit using a delay circuit, FIG. 5 shows a circuit configuration diagram of a conventional example, and FIG. 6 shows an operation timing diagram 1- of the conventional example. In the figure, l is a first delay circuit, 2 is a frequency multiplier, 3 is a second delay circuit, 4 is a frequency divider, 10 is a pattern generator, 2o is a test target, 4.30 is a delay circuit, 11 is a resistor, 12 is a capacitor,
13 and 14 indicate buffers. 〔Effect of the invention〕

Claims (1)

[Claims] A first delay circuit (1) having a CR circuit configuration, a frequency multiplier circuit (2) that includes the first delay circuit and doubles the frequency of the input signal, and a frequency multiplier circuit (2) that doubles the frequency of the input signal. It consists of a second delay circuit (3) with a CR configuration that can change the delay time, and a frequency divider circuit (4) that halves the frequency of the delayed multiplied signal and returns it to the original frequency. The signal and the delayed multiplied signal are input to a frequency dividing circuit (4), and a delayed signal synchronized with the rising and falling edges of the input signal is sent out from the frequency dividing circuit (4). A delay circuit whose duty does not change.