JPH02183354A - Overlap detector - Google Patents

Abstract

PURPOSE:To decrease the number of cores in an extended bus and to improve a noise-proof characteristic by inputting an overlap signal from a host extended unit, sending the signal to a low-order extended unit and sending the overlap signal of the self-unit to an I/O fundamental unit. CONSTITUTION:Respective extended units 20a-20n are equipped with a unit number register 22, unit number set circuit 23, unit discrimination part 24 and logical circuit 21. An overlap signal OVLPN is inputted from the host extended unit and sent to the low-order extended unit and an overlap detection signal OVLAP of the self-unit is sent to an I/O fundamental unit 10. Thus, since the number of the cores used for an extended bus 30 in order to detect overlap is two enough for OVLAP and OVLPO, the number of the cores is fixed regardless of the increase or decrease of the extended unit number and since the number of the cores is small, the noise-proof characteristic is improved. Then, reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an overlap detection device used in a remote input/output system of a programmable controller.

B9 Summary of the Invention In an apparatus that connects a plurality of expansion units to an input/output (hereinafter referred to as I10) basic unit, an overlap signal is input from the upper expansion unit, the overlap signal is sent to the lower expansion unit, and the own unit By configuring the I10 basic unit to send an overlap signal to the 110 basic unit, the number of expansion buses connecting the I10 basic units to each expansion unit can be reduced, and the noise resistance characteristics can be improved.

C4 Conventional technology In a programmable controller such as a remote control system, the control unit (CPU
)I is connected to a plurality of I10 basic units 2 via a bus 3', and in order to further increase the number of input/output points, one I10 basic unit 2 is connected to a plurality of expansion units)4 (4,
a to 4n) are connected via an expansion bus 5.

Figure 4 shows I10 basic unit 2 and expansion units 4a to 4.
This figure shows the state of the expansion bus 5 that connects the

Each expansion unit 4a to 4n is provided with a unit number setting circuit 41 for setting a unique unit number, and a unit number status register 42 for reading address setting values.
Between 2 and ■10 basic unit 2 is the select signal C8I~
They are connected by core wires for transmitting and receiving CSn.

D1 Problem to be Solved by the Invention Each expansion unit 4a to 4n has a unit number setting circuit 4.
1, each address is set, but the settings may be incorrect (overlap). Therefore, the I10 basic unit 2 reads the address written in the status register 42 for each of the expansion units 4a to 4n using the select signal C91=CSn, and determines whether or not there is an overlap. However, according to this method, in order to detect overlap, a core wire for C9I-C9n is required, and this core wire must be used as the number of expansion units increases, and as the number of core wires increases, Noise resistance characteristics deteriorate and reliability deteriorates. Furthermore, there is a problem in that it is impossible to connect connectors using the same pin number, which may cause erroneous connections.

21 Means for Solving the Problems This invention provides a unit number register in which unit numbers are written in a batch by I10 basic unit), and a unit number that is set respectively in the unit number written in this register. A unit number discriminator for comparison is provided in each extension register. Furthermore, each extension register has
Input the overlap signal from the upper expansion unit,
Sends an overlap detection signal to the lower expansion unit.

At the same time, the overlap detection signal of the own unit is
0 basic unit.

The F5 effect unit number determination section determines whether or not the own unit is selected, and generates an overlap detection signal when the own unit is selected and the upper expansion unit is selected.

Further, the overlap signal is output when the own unit is not selected and the upper expansion unit is not selected.

G Embodiment FIG. 1 shows an embodiment of the present invention, in which IO is I1
0 basic unit) A plurality of these units are connected to the control section I via the bus 3 as in FIG. 20a
~20n are expansion units, each unit has an expansion bus of 30
I10 is connected to the basic unit 10 through the I10. Note that this connection includes a route for sending and receiving data, addresses, and control signals, and a route between the logic circuit 21 installed in each expansion unit and the expansion module section 11 of the I10 basic unit 10.

FIG. 2 shows the overlap detection circuit of each expansion unit 20 (20a to 20n).

22 is a unit number register, I10 basic unit I.
Address signals from 10 are written.

23 is a unit number setting circuit for setting the number of the own unit. Reference numeral 24 denotes a unit determination unit, which outputs a signal 5ELECT when the address written in the register 22 and the unit number set by the unit number setting circuit 23 match.
to the logic circuit 21.The logic circuit 21 outputs a signal of level I] to the logic circuit 21.The logic circuit 21 outputs a signal of level I] to the logic circuit 21.The logic circuit 21 outputs an I10 basic unit 10 or an expansion unit connected to an upper level on the I10 basic unit side from the perspective of its own unit, for example, if its own colon unit is 20b. Ba 20
The overlap output 0VLPN from the unit a is ANDed with the 5ELECT signal of its own unit, and the overlap output 0VLPO is output from the lower expansion unit 20.
(1) A gate section G1 for outputting the overlap detection signal 0VLAP to the 10 basic units IO.

The logic for detecting overlap in this logic circuit 21 is based on the truth table shown below.

The operation of the present invention configured as described above will be explained.

Between the control unit l and the I10 basic unit 10, the bus 3
Signals are exchanged via the I10 basic unit IO
Based on signals from the control unit 1, signals are exchanged with each of the expansion units 20a to 20n via the expansion module.

In such a case, overlap is detected as follows.

When an address signal (unit number) is sent from the I10 basic unit 10, it is written into the unit number register 22 of each expansion unit 202L to 20n all at once. The written unit number A is compared with the own unit number B set in advance by the unit number setting circuit 23 in the unit number discrimination section 24, and when A=B matches, it is determined that the own unit has been selected. The “H” level 5ELECT signal shown in FIG. The logic circuit 21 receives the overlap human input OVLPN from the upper expansion unit, and inputs the OVLPN so that the overlap output 0VLPO is output to the lower expansion unit.
N and OV L P O are connected in series, 0VL
The PO notifies the extension unit below the position where the knit is placed whether or not the mortar unit is currently selected. Therefore, 0VLPN is a signal indicating the state of a unit higher than its own unit.

The logic for detecting and canceling the overlap in this logic circuit 21 is based on the truth table described above.
The L PO signal outputs an "L" level signal only when the own unit is not selected and the 4th-ranked unit is also not selected.

In addition, the OV L A P signal is "L" only when the own unit is selected and the "-" unit is selected.
Output level signal.

For example, if the expansion unit 20b is selected now,
5ELECT becomes “”I-Lebel, Kate Gl, G
2. Gate G2 has 0VLPN signal “■4
The "L" level signal is output to the OVLAP I/O basic unit number indicating that it has been selected based on the "level" condition, but the gate G1 outputs the "'H" level signal 0.
The VLPO is sent to the lower expansion unit 20c. On the condition that 20b is selected, the expansion unit 20C, when its own unit 20c is selected next, similarly outputs a signal OV L A P of "I," level to the I10 basic unit IO, and at the same time, "H" level signals OVT, PO for the lower expansion unit 20d
Output.

Thereafter, in the same manner, the I10 basic unit) 10 simultaneously writes unit numbers to all expansion units 20a to 2On, sequentially changes the selected unit number, and correspondingly notifies each expansion unit that it has been selected sequentially. Overlap is detected by determining whether the signal 0VLAP is output.

I] Effects of the Invention [2] According to the present invention, the core wire used in the expansion bus 30 for detecting overlap is an OVL AP.
Since only two cables are required, one for 0VLPO and one for 0VLPO, the number of expansion units is constant regardless of the number of expansion units, and commercially available general-purpose cables can be used as they are.Also, since the number of core wires is small, noise resistance characteristics are improved. The reliability of the device is miraculous.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an overlap detection circuit diagram in an expansion unit of the present invention, and FIG. 3 is a diagram of a remote I10 system 11 of a programmable controller for explanation. 4 are diagrams of conventional overlap detection circuits. l...Control unit, IO/I10 basic unit, 2゜a~
2On...Extension unit, 21, logic circuit, 22...
- Unit number register, 23...Unit number setting circuit, 24...Unit discrimination section. 2 people outside

Claims (1)

[Claims] (1) In a device that has a control unit and an input/output basic unit, and connects multiple expansion units from this unit via an expansion bus, a unit number register in which the unit number is written to each unit by the input/output basic unit. , a unit number setting section that sets a number unique to each expansion unit, and a unit number determination section that compares and determines the unit number set by this setting section and the unit number written in the unit number register. Provided in the expansion unit, for inputting the overlap signal from the higher-order expansion unit, sending the overlap detection signal to the lower-order expansion unit, and sending the overlap detection signal of the own unit to the input/output basic unit. An overlap detection device characterized in that each expansion unit is provided with a logic circuit.