JPH02183627A - D/a converter - Google Patents

Abstract

PURPOSE:To improve response speed without losing the resolution by extracting the high-order prescribed bit of an added data obtained by an adder means and outputting the data of prescribed bit to a pulse width signal conversion means. CONSTITUTION:The converter consists of a microprocessor 10 composed of a digital circuit 1, a random number signal generating means 2, an adder means 3 and a prescribed bit extraction means 4, a pulse width signal generating means 5 and a smoothing circuit 6. When a random number signal is added to a data to be converted, the data to be converted is minutely fluctuated in the range of fluctuation of the random number signal. When the high-order prescribed bit of the data adding the minute fluctuation is extracted and converted into a pulse width signal, even if the data to be converted is the same, the converted pulse width is slightly fluctuated at every period. Plural pulse width signals arranged in time series are smoothed by the smoothing circuit 6. Thus, it is possible to quicken the response speed without losing the resolution.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is a D/A conversion method in which a digital signal obtained by calculation by a microprocessor is converted into a pulse width signal, and then converted into an analog signal through a smoothing circuit. Regarding equipment.

<Prior Art> FIG. 3 is a conceptual diagram showing an example of a conventional D/A converter of this type. In the figure, 10 is a microprocessor that outputs a digital signal, 20 is an l/A converter that converts the digital signal into a pulse width signal (analog signal), and 30 is a smoothing circuit that smoothes the pulse width signal to obtain an analog signal. It is.

In the device configured in this way, the resolution of the obtained analog signal depends on the pulse width resolution (minimum pulse width) that enters the D/A converter 20.

Therefore, to increase analog resolution, either lengthen the pulse period or increase the pulse resolution (D/
There are two ways to do this: (increase the reference tarok frequency inside the A converter).

<Problems to be Solved by the Invention> However, when the pulse period is lengthened, the time constant in the smoothing circuit increases and the response characteristics worsen, so it is necessary to increase the reference clock frequency inside the D/A converter. This means that there are operating limits depending on the circuit elements used.

The present invention has been made in view of these points, and its purpose is to provide a D/A with fast response speed without impairing resolution.
The objective is to realize a conversion device.

Means for Solving the Problems> The present invention to solve the above problems provides a pulse width signal converting means for converting a digital signal to be converted into a pulse width signal, and a means for smoothing the pulse width signal to generate an analog signal. A D/A converter equipped with a smoothing circuit that generates a random number signal, a random number signal generating means for generating a random number signal, an adding means for adding digital data to be converted and a random number signal from the random number signal generating means, and a and a predetermined bit extracting means for extracting a predetermined upper bit of the obtained addition data and outputting the data of the predetermined bit to the pulse width signal converting means.

<For n:> When a random number signal is added to the data to be converted, the data to be converted slightly fluctuates within the variation range of the random number signal. When the data obtained by adding up this minute variation is extracted to the upper predetermined pitch 1 and converted into a pulse width signal, the converted pulse width varies slightly every cycle even if the data to be converted is the same. Become something. By averaging these plurality of pulse width signals arranged in time series using a smoothing circuit, it becomes possible to increase the response speed without impairing the resolution.

<Example> Embodiments of the present invention will now be described in detail with reference to the ten drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a digital circuit that outputs a digital signal to be converted, 2 is a random number signal generation means, and 3 is a summation of one digital word output from the digital circuit 1 and a random number signal from the random number signal generation means 2. addition means to
Reference numeral 4 denotes a predetermined pick l-extracting means for extracting upper predetermined picks 1 to 1 of the addition data from the adding means 3.

Reference numeral 5 represents a pulse width signal generating means for converting the extracted predetermined bits of digital data into a pulse width signal, and 6 represents a smoothing circuit for smoothing the converted pulse width signal into an analog signal.

Here, the digital circuit 1, the random number signal generation means 2, the addition means 3, and the predetermined pitch extraction means 4 all have the following characteristics:
It is assumed that this is realized by a program within the microprocessor 10.

The operation of the device configured in this way will be described next.

FIG. 2 is a flowchart showing an example of an operation performed by the microprocessor 10, for example, every 2 ms.

First, the microprocessor 10 outputs, for example, 16-bit digital data XL6 obtained by calculation (step 1). This operation is performed by the digital circuit 1 in FIG. 2 outputs random data di in the range of 0 to 15, for example (
Step 2).

The adding means 3 adds the digital data X16 and the random data di, and outputs the added data
).

Xo16=X16modi (1) The predetermined biyh extraction means 4 extracts this addition data X.

16 manually, and the upper 12 bits of this data
12 and outputs this 12-pips 1-data X12 to the pulse width signal generating means 5 (step 4.5).

The pulse width signal generating means 5 outputs 1 pulse width signal every 2 mS.
Based on the 2-pi1-data, it is converted into a pulse width signal with a resolution of 12 bits per cycle and output to the smoothing circuit 6.

The smoothing circuit 6 smoothes this pulse width signal into an analog signal, but by averaging 16 pulse width signals adjacent to each other in time series, this analog signal has one cycle of 16 pulse width signals.
This is similar to the pulse width signal output with bit resolution.

For example, suppose that the 16-bit data output from the digital circuit 1 is represented by r 1234 H, and then [0
If random data represented by ~FHj are added, the top 12 pieces of data are extracted, and 16 pieces of these extracted data are added, the result is as follows.

r1234H” → 123H + 1124H + 123H + 12
3H+123H+123H +124H-+-123H+123H 123H+123H+123H +124H+123H+124H +1238 1 2 3 Hx CH+ 1 2 4 Hx
4 H= 1234 H As is clear from the above equation, 12-bit data r
1231 (The distribution of J and rl 24HJ will be random.

Therefore, even though the pulse width signal generating means 5 inputs 12 bits data and converts it into a pulse width signal,
An analog signal obtained by averaging a plurality of pulse width signals therefrom corresponds to a 16-bit 1-resolution.

Further, in the pulse width signal generating means 5, if the minimum pulse width of the output pulse is, for example, 0.5 μs, the deviation is 1
When inputting 6-bit data and outputting a pulse width signal based on this data, the pulse period 'I' 16 becomes T16 = 0.5 μs x 2'' = 32 mS. When the data is converted into 12-bit data and a pulse width signal is output based on this data, the pulse period 1'12 becomes Tl2=0.5 μsX2=2 mS.

Therefore, in this case, it is possible to increase the response speed by about 16 times while maintaining the same resolution.

<Effects of the Invention> As described above in detail, according to the present invention, a D/A converter can be realized which has a high response speed without impairing resolution, and therefore can reduce the clock time.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing an example of the operation performed by the microprocessor in FIG. 1, and FIG. 3 is a conventional D
FIG. 2 is a conceptual configuration diagram showing an example of a /A converter. Prisoner J 1...Digital circuit, 2...Random number signal generation means,
3... Adding means, 4... Predetermined bit extraction means, 5.
...Pulse width signal generating means, 6...Smoothing circuit, 10.
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Claims (1)

[Scope of Claim] A D/A converter comprising a pulse width signal conversion means for converting a digital signal to be converted into a pulse width signal, and a smoothing circuit for smoothing the pulse width signal to obtain an analog signal, comprising: Random number signal generation means for generating a signal; Addition means for adding the digital data to be converted and the random number signal from the random number signal generation means; A D/A conversion device comprising: predetermined bit extraction means for outputting predetermined bit data to the pulse width signal conversion means.