JPH02185174A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To reduce a fixed pattern noise by rocking electric charges to be added in a vertical shift register by plural bits in a solid-state image pickup element where an electric charge from a photoelectric conversion element is transferred for plural number of times to the vertical shift register during one vertical period and summed therein. CONSTITUTION:A 2nd vertical shift register 8 is provided so as to be in connection with one end of a 1st vertical shift register 2 and both shift registers 2, 8 are coupled electrically. Then the electric charge transferred from the 1st vertical shift register 2 to the 2nd vertical shift register 8 is transferred to a horizontal shift register 9 one by one line during the succeeding one vertical period and a signal is outputted externally from a charge detection section 10. Furthermore, the electronic charges to be added are rocked by plural bits in the vertical shift register 2. A dark current leading to a fixed pattern noise is averaged over plural bits by rocking plural bits of added electric charges in the vertical shift register in this way, thereby reducing the noise.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a solid-state imaging device using a charge transfer device.
In particular, the present invention relates to a solid-state imaging device that performs a so-called multi-strobe operation in which charges are added multiple times in a vertical shift register in one vertical period.

[Summary of the invention]

The present invention relates to a solid-state imaging device in which charges are transferred and added to a vertical shift register multiple times during one vertical period from photoelectric conversion elements arranged in a matrix under the control of a transfer gate. By oscillating the signal by a plurality of bits within the shift register, fixed pattern noise can be reduced.

[Conventional technology]

As a solid-state imaging device suitable for use in motion analysis of high-velocity objects, etc., charges are added multiple times in one vertical cycle period using a vertical shift register (so-called multi-strobe operation).
A solid-state image sensor is known that performs
(See Publication No. 6388).

[Problem to be solved by the invention]

In such a solid-state imaging device in which charges are added a plurality of times in one vertical period, fixed pattern noise due to dark current of the vertical shift register becomes a problem.

That is, in the normal operation of a COD imager, the time it takes to accumulate image information consisting of a specific bit in the vertical shift register is short, and the averaging of that column is performed by the transfer of the vertical shift register. Therefore, fixed pattern noise (FPN) due to dark current in specific bits of the vertical shift register does not become a problem. However, in the solid-state image sensor that performs multi-strobe operation as described above, charge is accumulated in a specific bit of the vertical shift register from the first readout of one vertical cycle period, and the accumulation time is 1. Near the field,
Fixed pattern noise due to dark current becomes a problem.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, the present invention aims to provide a solid-state image sensor in which charge addition is performed multiple times in a vertical shift register in a vertical shift register, in which fixed pattern noise due to dark current is reduced. The purpose is to provide imaging devices.

[Means for Solving the Problems] In order to achieve the above object, the solid-state imaging device of the present invention includes a plurality of photoelectric conversion elements arranged in a matrix, and a vertical shift register that transfers charges in the vertical direction. , a transfer gate that controls the transfer of charges generated by each of the photoelectric conversion elements to the vertical shift register, and a horizontal shift register that transfers the charges in the horizontal direction. The structure of the vertical shift register described above may include a storage section, that is, the solid-state image sensor of the present invention may have an FIT
(frame interline transfer) type and IT (interline transfer) type, and the solid-state image sensor of the present invention transfers the charges accumulated in the photoelectric conversion element multiple times in one vertical cycle period. The charge is transferred to the vertical shift register through a gate, the charges transferred multiple times are added in the vertical shift register, and the charges are transferred to the horizontal shift register, and the charges to be added are added in the vertical shift register. It is characterized by swinging by multiple bits. Here, this fluctuation for a plurality of bits can be performed by performing the same number of transfers in one direction and the same number of transfers in the opposite direction. Further, in order to perform fluctuation for a plurality of bits, a redundant area of the vertical shift register may be provided so that the charge remains in the vertical shift register even when fluctuation is performed.

[Effect]

By oscillating the charge to be added by a plurality of bits within the vertical shift register, the dark current that leads to fixed pattern noise is averaged over a plurality of bits, thereby reducing noise.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment uses a frame interline transfer type (
Hereinafter, it will be referred to as the FIT type. ) is an example of a CCD solid-state image sensor that can perform so-called multi-strobe operation, and because the charge to be added is fluctuated by multiple bits within the vertical shift register, fixed pattern noise can be reduced. is to be done.

First, its configuration is as shown in FIG. Register 2 is arranged.

Between each photoelectric conversion element 1 and the first vertical shift register 2, the optical signal charge accumulated in each photoelectric conversion element 1 is transferred to the first vertical shift register 2.
A transfer gate 3 is arranged to control the transfer of the data to the vertical shift register 2. This solid-state image sensor has a horizontal overflow drain structure, and an overflow control gate 5 is disposed on the opposite side of the transfer gate 3 across the photoelectric conversion element l, and an overflow drain 4 is provided adjacent to the overflow control gate 5. is formed.

A second vertical shift register 8 is provided so as to be continuous with one end of the first vertical shift register 2.
and the second vertical shift register 2.8 are electrically coupled. This second vertical shift register 8 constitutes a storage section 7.

At the end of the second vertical shift register 8 opposite to the first vertical shift register 2, there is a horizontal shift register 9 electrically coupled to the second vertical shift register 8.
The horizontal shift register 9 outputs a signal for each horizontal line via the charge detection section 10.

Such an FIT type CCD solid-state image pickup device performs a multi-strobe operation using, for example, the signals shown in FIG.

FIG. 4 (al is a waveform diagram showing the vertical cycle period, and one cycle is determined by the vertical synchronization pulse Vsync. FIG. 4) shows the waveform of the signal Φorc supplied to the overflow control gate 5, It becomes low level 3 times within one vertical cycle period, and the period τ during which the level remains low
Accumulation of charge takes place at

This signal Φ. 1. When the level is high, unnecessary charges are swept out to the overflow drain 4.

FIG. 4(C) shows the signal Φ order supplied to the transfer gate 3. .

The waveform becomes high near the end of the charge accumulation period indicated by period τ. At this high level, the charge accumulated in the charge conversion element 1 is transferred to the first vertical shift register 2 via the transfer gate 3. Therefore, the relevant Figure 4 (
In the waveform C), charge is intermittently transferred three times and added in the first vertical shift register 2, respectively. Figure 4 (
d) shows the timing of transfer from the first vertical shift register 2 to the second vertical shift register 8, and the transfer is performed in a period T.

Note that the charge transferred to the second vertical shift register 8 is transferred to the horizontal shift register 9 by -line during one subsequent vertical cycle period, and a signal is output from the charge detection unit 10 to the outside. .

In the solid-state imaging device of this embodiment that performs such a multi-strobe operation, the charge to be added is further fluctuated by a plurality of bits within the vertical shift register. That is, the period t shown in FIG. 4(C) is the period from immediately after the charge is transferred from the photoelectric conversion element 1 to the first vertical shift register 2 until the next transfer. The first vertical shift register 2 performs a movement operation for a plurality of bits of charge to be added during the period t1.

Here, the above-mentioned moving operation will be briefly explained while focusing on the photoelectric conversion element PD, which constitutes one vertical shift register V□ as shown in FIGS. 1(A) to 1(D).

First, as shown in FIG. 1(A), from an arbitrary photoelectric conversion element PD, the photoelectric conversion element P
The charge e0 accumulated from D and to be added is transferred to the first vertical shift register VSII. Note that at this time, the level of the transfer gate TG is at a high level.

Next, as shown in FIG. 1(B), the level of the transfer gate TG is set to a low level, and the transfer of charges via the transfer gate TG is stopped. The first vertical shift register ■□ performs a charge movement operation in one direction (downward in the figure). This movement operation is performed during period t1 in FIG. 4(C), and is performed over, for example, n-bit registers (n is an integer of 2 or more).

Next, as shown in Figure 1 (C), in order to return the charge that has been moved across the register by n bits to its original position, the charge is transferred by the same n bits in the opposite direction (upward in the figure). . This causes the charge to return to the position of the register related to the photoelectric conversion element PD of interest, and when the charge to be added returns to its original position, the period 1. ends.

Next, as shown in FIG. 1(D), the photoelectric conversion element P
The charge e to be added is transferred from D again via the transfer gate TG.
1 is transferred to the first vertical shift register Vst, and the first
The amount of charge in the vertical shift register VSII is e, +e+
Here, if each charge eO+e1 is accumulated by the electronic shutter operation for only the period τ shown in FIG. 4(b), the multi-strobe operation is suitable for high-speed object analysis.

The movement operations shown in FIGS. 1A to 1D are performed according to the number of transfers in one vertical period (three times in the example of FIG. 4), and finally the first vertical shift register 2 The added charge is sent to the second vertical shift register 8 while being oscillated, and the charge is further taken out as a signal via the horizontal shift register 9 and the charge detection section 10.

FIGS. 5(A) to 5(C) are diagrams for schematically explaining the effects of the solid-state image sensor of this embodiment, and FIG. This is an example of fixed pattern noise caused by current.

When the movement operation for a plurality of bits as described above is performed, a filter effect as shown in FIG. 5(B) is obtained. That is, Fig. 1 (B), (C)
Assume that the movement operation shown in is performed on n-bit registers, and if the period from the transfer of the transfer gate 3 to the next transfer is t, then t 1 / n is the time when a specific charge is transferred to a specific charge. This is the time stored in the bit. Therefore, the time taken for dark current to occur from a specific focus point is reduced to /n, and the dark current is distributed to n bits of image information, reducing its level to n −+. Become. FIG. 5C shows an example of fixed pattern noise due to dark current in the first vertical shift register column after the movement operation for a plurality of bits, and the steep peak becomes a gentle curve.

The solid-state imaging device of this embodiment in which such fluctuations for a plurality of bits are performed in the first vertical shift register 2 can be provided with a redundant region 11 as shown in FIG. 2, for example. This redundant area 11 is located in the first vertical shift register 2 when the charges in the first vertical shift register 2 are moved by a plurality of bits.
This is an area for effectively moving the charges at the end of the vertical shift register 2. When moving the vertical shift register, the charges at the end can be effectively handled by forming the redundant region 11 of the vertical shift register on the opposite side. Conversely, if the charge is first moved by n bits from the first vertical shift register 2 to the second vertical shift register 8 side, a redundant area may be formed for this purpose, or a redundant area may be formed for that purpose. A part of the vertical shift register 8 may be used as the area 12 used for the movement operation.Of course, it is also possible to perform processing in which the charges at the end of the image section 6 are not made effective.

In the above-described embodiment, the number of transfers by the transfer gate 3 during one vertical cycle period is not limited to 3, but may be an integer of 2 or more, and the movement operation for swinging may also be performed in one direction. Rather than simply moving it and putting it back together again,
Movement operations that change direction by more than a degree are also possible.

Further, the overflow drain may have a vertical structure.

Second Embodiment This embodiment is an example of an interline transfer type (hereinafter referred to as IT type) CCD solid-state imaging device, as shown in FIG. In its configuration, photoelectric conversion elements 21 are arranged in a matrix, and vertical shift registers 22 are provided along one row of photoelectric conversion elements 21. One end of the vertical shift register 22 is electrically connected to the vertical shift register 2.
A horizontal shift register 23 connected to the terminal P of the horizontal shift register 23 is provided, and a signal is extracted by a charge detecting section 24 provided at the end of the horizontal shift register 23. Note that the transfer gate, overflow drain, and its overflow control gate are omitted for simplicity.

Even a solid-state imaging device with such an IT-type structure is capable of multi-strobe operation, and charges transferred to the vertical shift register 22 multiple times during one vertical period are transferred to the vertical shift register 22 in FIGS. As shown in D), the fixed pattern noise of the vertical shift register 22 due to dark current can be reduced by swinging by a plurality of bits.

Further, it is also possible to provide a redundant region 25 indicated by diagonal lines in FIG. 3, and the charge at the end of the vertical shift register 22 can also be effectively handled by the redundant region 25.

[Effects of the Invention] The solid-state image sensor of the present invention is an element that performs a multi-strobe operation in which charges are transferred and added to the vertical shift register multiple times in one vertical cycle period, and the charges to be added are The multiple bit wobbles within the vertical shift registers alleviate dark current concentration in particular registers and reduce fixed pattern noise.

[Brief explanation of the drawing]

FIG. 1 (A3-(D) is a schematic diagram for explaining the charge movement operation in the vertical shift register of an example of the solid-state image sensor of the present invention, and FIG. 2 is a schematic diagram of an example of the solid-state image sensor of the present invention. FIG. 3 is a configuration diagram showing the configuration of another example of the solid-state image sensor of the present invention, and FIG. 4 (al to (dl)
5(A) to 5(A) are waveform diagrams for explaining the so-called multi-strobe operation of an example of the solid-state image sensor of the present invention, respectively.
C) is an explanatory diagram for explaining the fixed pattern noise reduction effect of an example of the solid-state image sensor of the present invention. l...Photoelectric conversion element 2...First vertical shift register 3...Transfer gate 4...Overflow drain 5...Overflow control gate 8...Second vertical shift register 9...Horizontal Shift register 10...Charge detection unit Patent applicant Akira Kobe, patent attorney representing Sony Corporation (2 others) IT %! Figure 3 Ma IL + strobe light

Claims (1)

[Scope of Claims] A plurality of photoelectric conversion elements arranged in a matrix, a vertical shift register that transfers charges in the vertical direction, and control of transfer of charges generated by each of the photoelectric conversion elements to the vertical shift register. and a horizontal shift register that transfers charge in the horizontal direction, and transfers the charge accumulated in the photoelectric conversion element in one vertical period to the vertical shift register via the transfer gate multiple times. , in a solid-state imaging device in which charges transferred multiple times are added in the vertical shift register and transferred to the horizontal shift register, the charges to be added are oscillated by a plurality of bits in the vertical shift register. A solid-state image sensor featuring: