JPH0218621A - Data processor - Google Patents

Abstract

PURPOSE:To reserve the writing jobs to two optional registers without adding any hardware by dividing an instruction code into the step codes including the register designating fields of each register in case two writing register designating fields are included in an instruction code serving as one instruction decoding process unit. CONSTITUTION:When an instruction code including two register designating fields and performing a writing job into an instruction code 211 serving as one instruction decoding unit is decoded, a 1st decoding result including the reservation information on a 1st register is outputted via an instruction decoding stage 202. Then a 2nd decoding result including the reservation information on a 2nd register is outputted. Thus the registers are reserved for both decoding results respectively. The processing result obtained to the 1st decoding result at an address calculation stage 203 is not outputted to a stage 204 and subsequent stages. While only the processing result to the 2nd decoding result is outputted to the subsequent stages 204 and 205 respectively. Thus the writing reservation is ensured to two optional registers without adding any hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that achieves high processing performance through an advanced pipeline processing mechanism.

[Prior Art] FIG. 31 is a schematic diagram showing the configuration of a typical pipeline stage of a conventional data processing device.

In the figure, 71 is an instruction fetch (IP) stage;
2 is an instruction decode (D) stage, 73 is an operand address calculation (A) stage, 74 is an operand fetch (F) stage, 75 is an instruction execution (E) stage, 76
is the operand light (W) stage.

Next, the operation will be explained. The pipeline mechanism of the data processing device shown in FIG.
．． D stage 72 for analyzing instruction data. A stage 73 for calculating addresses of operands, etc. F stage 74 for fetching operand data. It is composed of 6 pipeline stages: an E stage 76 for processing data, and a W stage 760 for writing operand data, and each stage can process different instructions simultaneously. However, if a conflict occurs when accessing an operand or memory, processing at a stage with a lower priority is stopped until the conflict is resolved.

As described above, in a pipelined data processing device, processing is divided into multiple stages according to the flow of data processing, and each stage is operated simultaneously.
By shortening the average processing time required for each instruction, the overall processing time is shortened and performance is improved.

Conventional pipeline processing is as described above, but one problem that must be taken into account when configuring pipeline processing is conflicts in the resources used. A specific example is a register conflict.
If the contents of the register referenced during address calculation are rewritten in an instruction that is being processed in advance in the pipeline, an incorrect result will be produced.

In order to solve these problems, a register conflict check means has been proposed, for example, as disclosed in Japanese Patent Application No. 144394/1982.

The operation of the invention disclosed in Japanese Patent Application No. 62-144394 will be explained. For registers whose values may be rewritten in the execution stage, a write reservation for the registers is made according to the address calculation result in the address calculation stage. This write reservation information is held until the writing in the execution stage is completed and the write reservation is canceled. On the other hand, when calculating an address, it is checked whether the register to be referenced is likely to be rewritten by an instruction that is being processed in advance in the pipeline. If there is a possibility of rewriting, processing is temporarily stopped, writing to the register by the preceding processing instruction is completed, and the register is referenced after the write reservation is canceled.

By performing such processing, patent application No. 621443
The invention of No. 94 guarantees that the correct register value is referenced when calculating an address. In this example, register write reservation can specify only one general-purpose register or other specific register groups (including all registers).

[Problems to be Solved by the Invention] As described above, in the pipeline processing mechanism of a conventional data processing device, when two arbitrary registers to be rewritten are specified in the instruction code that is processed at once in the instruction decode stage. , it is necessary to reserve all registers for writing, or to add hardware to reserve two arbitrary write registers at once, which increases the complexity of the configuration.
This has led to an increase in hardware.

An object of the present invention is to provide a data processing device that can reserve writing to two arbitrary registers without adding any hardware as described above.

[Means for Solving the Problems] When the instruction decoding stage processes an instruction having first and second register designation fields in which operands are written, the data processing device of the present invention has the following advantages: a first unit processing code containing information;
A second unit processing code including information of the second register specification field is generated. Furthermore, in the address calculation stage, pipeline processing units having instruction information only for register reservation processing are absorbed into one unit processing code.

Y effect] In the data processing device of the present invention, when decoding an instruction code that includes two register specification fields for writing in one instruction decode unit, first, in the instruction decode stage, the first The first decoding result including the register reservation information is output, and then the second decoding result is output.
A second decoding result including reservation information for each register is output, and one register is reserved for each register. Further, the processing result for the first decoding result in the address calculation stage is not output to the next stage and subsequent stages, and only the processing result for the second decoding result is output to the next stage and subsequent stages.

[Embodiments of the Invention] The present invention will be described in detail below based on drawings showing embodiments thereof.

(1) 1. Instruction formant of data processing device of the present invention”
The instructions of the data processing device of the present invention have a variable length in units of 16 bits, and instructions with an odd number of bytes are not used.

The data processing device of the present invention has an instruction format system specially devised for the purpose of converting high-frequency instructions into short formants. For example, for 2-operand instructions, there is a general format that basically has a configuration of "4 bytes + extension" and all addressing modes can be used, and a general format in which only frequently used instructions and addressing modes can be used. There are two abbreviated formats.

The meanings of the symbols appearing in the instruction form of the data processing device of the present invention are as follows.

: Part where operation code is entered #: Part where literal or immediate value is entered Ea: Part that specifies the operand in the 8-bit I-ship-shaped addressing mode Sh: Part that specifies the operand in the 6-bit abbreviated addressing mode Rn ; In the partial format in which operands on registers are designated by register numbers, as shown in FIG. 3, the right side is 1, the SB side is the higher address. The instruction format cannot be determined without looking at the two bytes of address N and address N+1, but this is based on the assumption that instructions are always fetched and decoded in 16-bit (2-hyde) units, as mentioned above. This is because there is.

In the data processing apparatus of the present invention, in any format, the extended part of Ea or sh of each operand is always located immediately after the halfword containing the basic part of Ea or sh. This overrides any immediate data or extensions of the instruction implicitly specified by the instruction. Therefore, 4
For instructions larger than a byte, the operation code of the instruction may be divided by the extension part of Ea.

Further, as will be described later, even when an extension part is added to the extension part of Ea in the multi-stage indirect mode, that part is given priority over the next instruction operation code. For example, the first
Halfword contains Eal, second halfword contains Ea
Consider the case of a 6-height instruction containing 2 and up to the third half-word. Since the multi-indirect mode is used for Eal, assuming that the multi-indirect mode extension is included in addition to the normal extension, the actual instruction bit pattern is the first halfword of the instruction (including the basic part of Eal), The order is the extension of Eal, the multi-indirect mode extension of Eal, the second halfword of the instruction (including the base of Ea2), the extension of Eal, and the third halfword of the instruction.

(],,1) rReduced 2-Operand Instruction" FIGS. 4 to 7 are schematic diagrams showing the abbreviation formant of the 2-operand instruction.

FIG. 4 is a schematic diagram showing the formant of an operation instruction between memory registers. This format includes L-format, where the source operand side is memory, and S-format, where the destination operand side is memory.
There is a t.

In L-format, sh represents a source operand designation field, Rn represents a destination operand register designation field, and RR designates the sh operand size. The size of the destination operand located on the register is fixed at 32 bits. Sign extension is performed when the size of the register side and the memory side are different and the size of the source side is small.

In the S-format, sh represents a destination operand designation field, Rn represents a source operand register designation field, and RR represents sh operand size designation. The size of the source operand located on the register is fixed at 32 bits. If the size of the register side and the memory side are different and the size of the source side is large, the overflow portion is truncated and an overflow check is performed.

FIG. 5 is a schematic diagram showing the format (R-format) of an inter-register operation instruction. Rn is a destination register designation field, and Rm is a source register designation field. The operand size is only 32 bits.

Figure 6 is the format of literal-memory operation instructions)
(Q-format). The question is the destination operand size specification field, #I
# is a literal source operand designation field, and sh is a destination operand designation field.

Figure 7 shows the formant (1-
FIG. MM is an operand size specification field (common for source and destination), and sh is a destination operand specification field. The size of the immediate value of L-format is 8.16.32 bits, which is the same as the size of the destination operand, and zero extension and sign extension are not performed.

(1, 2) r-ship shape 1 operand command” Figure 8 shows 1
Single film format of operand instruction) (Gl-for
FIG. The question is the operand size specification field. Some G1forvnat instructions have extensions in addition to the Ea extension. There are also some commands that do not use .

(1, 3) r-Ship-shaped 2-operand Instruction" FIGS. 9 to 11 are schematic diagrams showing the single-layer format of the 2-operand instruction. This formant contains 8
This is an instruction that has a maximum of two operands in single-layer addressing mode specified by bits. The total number of operands itself may be three or more.

FIG. 9 is a schematic diagram showing the format (G-format) of an instruction whose first operand requires memory reading. EaM is a destination operand specification field, EaR is a destination operand size specification field, EaR is a source operand specification field, and RR is a source operand size specification field. Some G-format instructions have extensions in addition to the Ea or EaR extensions.

FIG. 10 is a schematic diagram showing the format (E-format) of an instruction whose first operand is an 8-bit immediate value.

EaM is a destination operand designation field, EaM is a destination operand size designation field, and #t... is a source operand value.

Although E-format and I-format are similar in function, they are very different in terms of way of thinking. Specifically, E-format only has two operands.
It is a derivative of the film format (G-format), and the source operand size is fixed at 8 bits, and the destination operand size can be selected from 8/16/32 bits. In other words, E-format is based on the premise of operations between different sizes, and the 8-bit source operand is zero-extended or sign-extended to match the size of the destination operand. On the other hand, I-format is a shortened form of an immediate value pattern that is frequently used especially in transfer instructions and comparison instructions, and the size of the source operand and destination operand are equal.

FIG. 11 is a schematic diagram showing the format (GA-format) of an instruction whose first operand is only address calculation. EaW is a destination operand specification field, OPEN is a destination operand size specification field, and EaA is a source operand specification field. The execution address calculation result itself is used as the source operand.

FIG. 12 is a schematic diagram showing the formant of a short branch instruction. cccc is a branch condition specification field, and disp:8 is a displacement specification field with respect to the jump destination. In the data processing device of the present invention, when specifying a displacement with 8 bits, the specified value in bisotobakun is doubled and the displacement is value.

(1, 4) r Addressing Mode There are two methods for specifying the addressing mode of the data processing apparatus of the present invention: an abbreviated form in which the addressing mode is specified using 6 bits including registers, and a general form in which the addressing mode is specified using 8 bits.

If an undefined addressing mode is specified, or if a semantically inappropriate combination of addressing modes is specified, a reserved instruction exception will occur in the same way as when an undefined instruction is executed. , exception handling is triggered.

This applies when the destination is in immediate mode, or when immediate mode is used in the addressing mode specification field that should involve address calculation.

The meanings of the symbols used in the formant diagrams are as follows.

Rn: Register specification mem EA: Memory contents of the address indicated by EA (Sh): Specification method in 6-hit abbreviated addressing mode (Ea): Specification method in 8-hit general addressing mode Broken line in the format diagram The area surrounded by indicates an extension.

(1,4,1) r Basic Addressing Mode The data processing device of the present invention supports various addressing modes. Among them, the basic addressing modes supported by the data processing device of the present invention include register direct mode, register indirect mode, register relative indirect mode, immediate mode, absolute mode, PC (program count) relative indirect mode, and stack point. There are push mode and stack mode.

In register direct mode, the contents of the register are used as the final operand. A schematic diagram of FORMANO 1~ is shown in FIG. Rn indicates the number of a general-purpose register.

In register indirect mode, the operand is the contents of the memory whose address is the contents of the register. A schematic diagram of the fomanoto is shown in Fig. 14. Rn indicates the number of a general-purpose register.

In register relative indirect mode, the displacement value is 1.
There are two types depending on whether it is 6 bits or 32 bits. 16 bits or 32 bits for register contents, respectively.
The operand is the contents of the memory whose address is the value plus the bit displacement value. A schematic diagram of the format is shown in FIG. Rn indicates the number of a general-purpose register. disp:16 and disp:32 each indicate a 16-bit displacement value or a 32-bit displacement value. The displacement value is treated as having a sign.

In the immediate mode, the bit pattern specified in the instruction code is treated as a binary number and used as an operand. A schematic diagram of the format is shown in FIG.

imm-data indicates an immediate value. The size of imm-data is specified in the instruction as the operand size.

In absolute mode, the address value is indicated by 16 bits or 32
There are two types depending on whether it is indicated by a bit. Each operand is the contents of the memory whose address is a 16-bit or 32-bit pattern specified in the instruction code. A schematic diagram of the format is shown in FIG. a
bs:16 and abs:32 indicate a 16-bit or 32-bit address value, respectively.

When an address is indicated by abs:16, the specified address value is sign-extended to 32 bits.

There are two types of PC relative indirect modes depending on whether the displacement value is j6 bits or 32 bits. FIG. 18 shows a schematic diagram of a six-format node whose operands are the contents of a memory whose addresses are the contents of the program counter plus a 16-bit, 1, or 32-bit displacement value. disp: 16 and disp
: 32 indicates a 16-bit displacement value or a 32-bit displacement value, respectively. Displacement values are treated as having a sign of "I".

In PC relative indirect mode, the referenced program counter value is the start address of the instruction containing the operand. When the value of the program counter is referenced in the multi-stage indirect addressing mode, the first address of the instruction is similarly used as the PC-relative reference value.

The stack pop mode uses the contents of the memory whose address is the contents of the stack pointer (S11) as the operand. After accessing the operand, increment the stack pointer by the operand size.

For example, when handling 32-bit data, SP is updated (incremented) by +4 after operand access. It is also possible to specify stack pop mode for operands of size B and H, each with SP +1.
It is updated (incremented) by +2. A schematic diagram of the format is shown in FIG. A reserved instruction exception is generated for operands in which stack pop mode 1' has no meaning.

Specifically, the reserved instruction exception is the stack pop mode specification for the write operand and read-modify-write operand.

In the stack bush mode, the operand is the contents of the memory whose address is the contents of the stack pointer resolved to the operand size. In stack bush mode, the stack pointer is decremented before operand access. For example, when handling 32-bit data, SP is updated (decremented) by -4 before operand access. It is also possible to specify stacked bush mode for operands of size B and H, and SP is updated (decremented +1) by -1 and -2, respectively. A schematic diagram of the format is shown in Figure 20. For those for which the stacked bush mode has no meaning, a reserved instruction exception is generated.

Specifically, the reserved instruction exception is the stack bush mode specification for the read operand and read-modify-write operand.

(], 4.2) Multi-stage indirect addressing mode No matter how complex addressing is, it is basically broken down into a combination of addition and indirect reference. Therefore, if addition and indirect reference operations are provided as addressing primitives and can be combined arbitrarily, any complex addressing mode can be realized. The multi-stage indirect adreno song mode of the data processing device of the present invention is an adreno song mode based on this idea. Complex addressing modes are particularly useful for inter-module data references or AI (artificial intelligence) language processing systems.

When specifying the multi-stage indirect addressing mode, the basic addressing mode specification field specifies one of three types of specification methods: register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute-based multi-stage indirect mode.

Register-based multi-stage indirect mode is an addressing mode in which the value of a register is used as the base value for multi-stage indirect addressing to be extended. A schematic diagram of the formant is shown in FIG. Rn indicates the number of a general-purpose register.

The PC-based multi-stage indirect mode is an addressing mode in which the value of the program counter is used as the base value for multi-stage indirect addressing to be extended. The second schematic diagram of the claw cloak
Shown in Figure 2.

The absolute Hayes multi-stage indirect mode is an addressing mode that uses zero as the base value of extended multi-stage indirect addressing. A schematic diagram of Formatsu 1- is shown in FIG.

The multi-stage indirect mode specification field to be expanded has a unit of 16 bits, and this is repeated any number of times.

Displacement addition and index register scaling (XI, X
2. X4. X8) and performs indirect reference to memory. A schematic diagram of the format of the multi-stage indirect mode is shown in FIG. Each field has the meaning shown below.

E-0: Continuation of multi-stage indirect mode E-1 End of near address calculation tmp ==> address of opera
nd■-0: No memory indirect reference tmp+disp+Rx*5cale==>tmpI-
1: Memory indirect reference memtmp+disp1Rx*5cale==>1.
mpM=0: Use <Rx> as index 1: Special index <Rx>-〇 Do not add index value (R
x=0) <Rx>-1 Use program counter as index value (Rx=PC) <Rx>=2- reserved D-0: Multiply the value of 4-bit field d4 in multi-stage indirect mode by 4 and output D4 is treated as a signed brace value and added to it, and is always multiplied by 4 regardless of the size of the operand.D=1: disp specified in the extension part of multi-stage indirect mode
x (16/32 bits is the displacement value, and the size of the extension to which this is added is specified in the d4 field. d4=o001 d:spx is 16 bits d4=o
o10 dispx is 32 bits xx; index scale (scale = 1/2/4/8) If the program counter is scaled by x 2 + × 4 + × 8, the intermediate value after the processing of that stage is completed. (
An undefined value is entered as tmp). Although the effective address IMed by this multi-stage indirect mode becomes an unpredictable value, no exception occurs. Do not specify scaling for the program counter.

The precision of the instruction formant in the multi-stage indirect mode is shown in FIGS. 25 and 26.

FIG. 25 shows a variation of whether the multi-stage indirect moat continues or ends.

FIG. 26 shows variations in the size of the disbracemen 1-.

If a multi-stage indirect mode with an arbitrary number of stages can be used, there is no need for the compiler to differentiate between cases based on the number of stages, which has the advantage of reducing the burden on the compiler. This is because even if the frequency of multiple indirect references is very low, the compiler must always be able to generate correct code. Therefore, any number of stages is possible in the format.

(1, 5) r Exception Handling” The data processing device of the present invention has abundant exception handling functions to reduce the software load. In the data processing device of the present invention, exception processing involves re-executing instruction processing (exceptions).
They are divided into three types and named: , those that complete instruction processing (traps), and interrupts. Furthermore, in the data processing apparatus of the present invention, these three types of exception handling and system failure are collectively referred to as BIT.

(2) "Configuration of Functional Blocks" FIG. 2 is a block diagram showing the configuration of the data processing device of the present invention.

Functionally, the inside of the data processing device of the present invention can be roughly divided into an instruction fetch unit 101. instruction decoding unit 102,
PC calculation section 103. Operand address calculation section 104 micro ROM section 105. Data calculation unit 106. It is divided into an external lotus interface section 107.

In addition, in FIG. 2, an address output circuit 108 for outputting an address to the outside of the CPU, and a data input/output circuit 109 for inputting/outputting data to/from the CPII are shown separately from other functional blocks.

(2, 1) r Instruction fetch unit The instruction fetch unit 101 includes a branch buffer, an instruction queue, its control unit, etc., and determines the address of the next instruction to be fetched and fetches the instruction from the branch buffer or memory outside the CPU. fetch. It also registers instructions to the branch buffer.

Since the branch buffer is small, it operates as a selective cache. The details of the operation of the branch buffer are described in detail in Japanese Patent Application No. 61-202041.

The address of the next instruction to be fetched is calculated by a dedicated counter as the address of the instruction to be input into the instruction queue. When a branch or a jump occurs, the address of a new instruction is transferred from the PCδ1 calculation unit 103 or the data calculation unit 106.

When fetching an instruction from a memory external to the CPU, the address of the instruction to be fetched is sent from the address output circuit 108 to the CPU via the external bus interface unit 107.
u output to the outside and fetch the instruction code from the data input/output circuit 109. Then, the instruction code to be decoded next among the output instruction codes is output to the instruction decoding unit 102.

(2, 2) r Instruction Decoding Unit” The instruction decoding unit 102 basically decodes instruction codes in units of 16 bits (halfwords). This block includes an FH-decoder for decoding the operation code contained in the first halfword, a second . An NFIIW decoder decodes the operation code included in the third halfword, and an addressing mode decoder decodes the addressing mode. These PIIW decoder, NF)tW decoder, and addressing mode decoder are collectively referred to as a first decoder.

A second decoder that further decodes the output of the FHW decoder or NFHW decoder to calculate the entry address of the micro ROM, a branch prediction mechanism that predicts branches of conditional branch instructions, and an address that checks pipeline conflicts when calculating operand addresses. A computational conflict checking mechanism is also included.

The instruction decode unit 102 converts the instruction code input from the instruction fetch unit 101 by θ every two clocks (one step).
~Decode 6 bytes at a time. Among the decoding results, information regarding the calculation in the data calculation section '1.06 is
The OM unit 105 outputs information related to operand address calculation to the operand address calculation unit 104, and the information related to pc calculation to the pc calculation unit 103.

(2, 3) ``Micro ROM section'' The micro ROM section 105 mainly includes a data calculation section 106.
It includes a micro RAM in which a micro program for controlling is stored, a micro sequencer, a micro instruction decoder, etc. 2 micro instructions from micro ROM
It is read out once per clock (1 step). In addition to the sequence processing indicated by the microprogram, the microsequencer accepts processing of exceptions, interrupts, and traps (these three are collectively referred to as El↑) using hardware. The micro ROM unit 105 also manages the store hardware. The micro ROM unit 105 receives flag information based on interrupts or operation results that do not depend on instruction codes, and outputs from the instruction decoding unit such as the output from the second decoder. The output of the micro-decoder is mainly output to the data calculation unit 106, but some information, such as other preceding processing stop information due to execution of a jump instruction, is also output to other blocks.

(2, 4) r Operand Address Subtraction Unit The operand address calculation unit 104 is hard-wired controlled by information related to operand address calculation output from the address decoder of the instruction decoding unit 102, etc. This block performs most of the processing related to operand address calculation. A check is also made to see if the memory access address and operand address for memory indirect addressing fall into the memory mapped I10 area.

The address calculation result is sent to the external bus interface section 107.
sent to. The values of the general-purpose registers and program counter necessary for address calculation are input manually from the data calculation section.

When indirect memory addressing is performed, the address output circuit 108 outputs the memory address to be referenced to the outside of the CPU through the external bus interface section 107, and the indirect address value input from the data input/output section 109 is fetched through the instruction decoding section 102. .

(2, 5) rPC calculation unit” The pc calculation unit 103 is hard-wired controlled by information related to PC calculation output from the instruction decoding unit 102, and divides the pc value of the instruction. The data processing device of the present invention has a variable length instruction code, and the length of the instruction cannot be determined unless the instruction is decoded. Therefore, the PC calculation unit 103 creates the pc value of the next instruction by adding the instruction length output from the instruction decoding unit 102 to the pc value of the instruction being decoded. In addition, the instruction decoding unit 10
2 decodes a branch instruction and instructs a branch at the decoding stage, the pc value of the branch destination instruction is calculated by adding the branch displacement instead of the instruction length to the pc value of the branch instruction. In the data processing device of the present invention, branching to a branch instruction at the instruction decoding stage is called pre-branch.

Regarding this pre-branch method, please refer to Japanese Patent Application No. 612045.
00 and Japanese Patent Application No. 61-200557.

The calculation result of the pc calculation unit 103 is output as the pc value of each instruction together with the instruction decoding result, and at the time of pre-branch, it is output to the instruction fetch unit 101 as the address of the next instruction to be decoded. It is also used as an address for branch prediction of the next instruction to be decoded by the instruction decoding unit 102.

The branch prediction method is described in detail in Japanese Patent Application No. 8394/1983.

(2, 6) r Data Operation Unit The data operation unit 106 is controlled by a microprogram, and uses registers and arithmetic units to execute operations necessary to realize the function of each instruction according to the output information of the micro ROM unit 105. When the operand to be operated on is an address or an immediate value, the address or immediate value calculated by the operand address calculation unit 104 is passed through the external lotus ink face unit 107 and obtained. Furthermore, when the operand to be operated on is in the memory outside the CPU, the address calculated by the address calculation unit 104 is sent to the address output circuit 1 by the bus ink face unit.
The data input/output circuit 09 outputs the data from the data input/output circuit 09 and outputs the operand from the memory outside the CPU.

Examples of arithmetic units include an ALU, a barrel shifter, a priority encoder or counter, and a shift register. The registers and the main arithmetic unit are connected by three hashes, and one microinstruction instructing one register-to-register operation is processed in two clocks (one step).

When it is necessary to access memory outside the CPU during data calculation, the address is output from the address output circuit 108 to the outside of the CPU through the external bus interface section 107 according to instructions from the microprogram, and the target data is output through the data input/output circuit 109. fetch

When storing data in a memory external to the CPU, an address is output from the address output circuit 108 through the external bus interface section 107, and at the same time, data is output from the data input/output circuit 109 to the outside of the CPU. In order to efficiently store operands, the data calculation unit 106
is equipped with a 4-byte store buffer.

When the data calculation unit 106 obtains a new instruction address by processing a jump instruction or processing an exception, it outputs this to the instruction fetch unit 101 and the PC calculation unit 103.

(2, 7) ``External Bus Interface Section'' The external bus interface section 107 controls communication on the external bus of the data processing apparatus of the present invention. All memory accesses are clock synchronized and take a minimum of 2 clock cycles (
It can be done in one step).

The instruction fetch unit 101 issues an access request to the memory.
Operand address calculation unit 104 and data calculation unit 10
arises independently from 6. External bus interface section 10
7 arbitrates these memory access requests. Furthermore, when accessing data at a memory address that straddles a 32-bit (1 word) aligned boundary, which is the data bus size that connects memory and the CPU, this block automatically detects that it straddles a word boundary. It is broken down into two memory accesses.

It also performs conflict prevention processing when the pre-fetch operand and store operand overlap, and bypass processing from the store operand to the fetch operand.

(3) “Pipeline mechanism” The pipeline processing function of the data processing device of the present invention is the first
As schematically shown in the figure.

Instruction fetch stage (IP
Stage) 201. Decode stage (D stage) 202 for decoding instructions. Operand address calculation stage (A stage) that calculates the address of the operand
203. Micro ROM access (especially R stage 20
6) and a part that performs operand brief fetching (particularly referred to as OF stage 207). A five-stage configuration of an execution stage (E stage) 205 for executing instructions is the basis of pipeline processing.

E stage 205 has a one-stage store bath sofa,
Some of the high-performance instructions pipeline the instruction execution itself, so there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and in theory the five stages operate completely independently.

Each stage can perform one process in a minimum of two clocks (one step). Therefore, ideally two clocks (
Pipeline processing progresses one after another for each step (1 step).

The data processing device of the present invention has some instructions that cannot be processed with just one basic pipeline process, such as memory-to-memory operations or memory indirect addressing, but the data processing device of the present invention can handle these processes. It is designed to perform pipeline processing as balanced as possible. An instruction having a plurality of memory operands is decomposed into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands, and pipeline processing is performed.

Regarding the decomposition method of pipeline processing units, please refer to the patent application 1986.
It is described in detail in No.-236456.

The information passed from the IF stage 201 to the D stage 202 is the instruction code 211 itself. D stage 20
The information passed from 2 to the A stage 203 is related to the operation specified by the instruction (referred to as the D code 212),
Things related to operand address calculation (code 2
13).

The information passed from the A stage 203 to the F stage 204 is an R code 214 that includes the microprogram entry address or microprogram parameters, and an F code 215 that includes the operand address and access method instruction information. .

The information passed from the F stage 204 to the E stage 205 is two types: an E code 216 including arithmetic control information and literals, and an S code 217 including operands or operand addresses.

An EIT detected at a stage other than the B stage 205 is a BIT until the code reaches the E stage 205.
Does not start processing. Only the instructions being processed in the E stage 205 are instructions in the execution stage, and the instructions being processed in the IF stage 201
This is because the instructions being processed between F stage 204 and F stage 204 have not yet reached the execution stage. Therefore, when a BIT is detected at a stage other than the E stage 205, its detection is recorded in the step code and only transmitted to the next stage.

(3,1) r pipeline processing unit” (3,1,1
) Classification of Instruction Code Fields The pipeline processing unit of the data processing apparatus of the present invention is determined using the characteristics of the instruction code format.

As described in Section +11, the instructions of the data processing device of the present invention are variable length instructions in units of 2 bytes, and basically the "2 byte basic instruction part + 0 to 4 byte addressing extension part" is divided into 1 to 3 An instruction is constructed by repeating it several times.

In most cases, the instruction basic part has an operation code part and an addressing mode specification part, and if index addressing or memory indirect addressing is required, a "2-hyde multi-stage indirect mode specification part" is used instead of the addressing extension part. Addressing extension part + 0 to 4 hides is optionally spaced. Also, depending on the command, 2 or 4
Hyde's command-specific extensions are added at the end.

The instruction basic part includes the instruction operation code, basic addressing mode, literal, etc. Addressing extensions include displacement, absolute address,
Either an immediate value or a displacement of a branch instruction. Instruction-specific extensions include a register map, immediate value specification for I-format instructions, and the like. FIG. 27 is a schematic diagram showing the characteristics of the basic instruction format of the data processing device of the present invention.

(3, 1, 2) Decomposition of instructions into r step code”
The data processing device of the present invention performs pipeline processing that takes advantage of the characteristics of the instruction format described above.

At the D stage 202, “2-byte instruction basic part → −0 ~
4-hide addressing extension, "multi-stage indirect mode specification part addressing extension," or instruction-specific extension are processed as one decoding unit.The decoding result of each time is called a step code, and from the A stage 203 onwards, this The step code is the unit of pipeline processing.The number of step codes is unique for each instruction, and if multi-stage indirect mode is not specified, one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes.Multi-stage When the indirect mode is designated, the step code increases accordingly.However, as will be described later, this is only at the decoding stage.

(3, 1, 3) ``Program counter management'' It is possible that all the step codes existing on the pipeline of the data processing device of the present invention are for different instructions, and therefore the value of the program counter is the same as the step code. managed separately. Every step code has the program counter value of the instruction that the step code is based on. The program counter value that accompanies the step code and flows through each stage of the pipeline is referred to as the step program counter (spc). The sPc is passed between pipeline stages one after another.

(3, 2) Processing of Each Pipeline Stage The turnout step codes for each pipeline stage are given names for convenience as shown in FIG. Further, the step code performs processing related to the operation code, and there are two series: a series that becomes the entry address of the microprogram and parameters for the E stage 205, and a series that becomes the operand for the microinstruction of the E stage 205.

(3, 2, 1) r Instruction fetch stage The instruction fetch stage (IF stage) 201 fetches instructions from memory or branch buffer and stores them in the instruction queue 3.
01 and outputs the instruction code to the D stage 202. Input to the instruction queue is performed in units of arranged 4 hides. When fetching an instruction from memory, a minimum of two clocks (one step) is required for every four aligned hides. If the branch buffer is hit, it can be fetched in one clock per four aligned bytes.

The output unit of the instruction queue is variable every 2 heights, and a maximum of 6 heights can be output during 2 clocks.

Further, immediately after a branch, it is also possible to bypass the instruction queue and directly transfer the 2 bytes of the instruction basic part to the instruction decoder.

Control of registering and clearing instructions in the branch buffer,
The IF stage 201 also manages the address of the pre-fetch destination instruction and controls the instruction queue.

BITs detected in the IF stage 201 include bus access exceptions when fetching instructions from memory, address translation exceptions due to memory protection violations, and the like.

(3, 2, 2) r instruction decode stage” instruction decode stage (D stage) 2o2 is IF stage 20
Decodes the instruction code input from 1. Decoding is performed by the FIIW decoder of the instruction decoding unit 102 and the NFII
- The first decoder 15, which is a combination of a decoder and an addressing mode decoder, is used to perform decoding once every two clocks (one step), and one decoding process consumes 0 to 6 bytes of instruction code (for RET instructions). Instruction codes are not consumed in output processing of step codes including return destination addresses, etc.).

In one decoding, the A stage 203 receives a control code and address modification information, which is an A code 213 as address calculation information, and a control code and 8-bit literal information, which is a D code 212 as an intermediate decoding result of an operation code. Outputs . At this time, part of the decoder result is latched into the launch circuit 17 as the intermediate code 16. The intermediate code 16 latched by the latch circuit 17 is given to the first decoder 15 again.

The D stage 202 also performs control of the PC calculation unit 103 for each instruction, branch prediction processing, prebranch processing for prebranch instructions, and instruction code output processing from the instruction queue.

EITs detected at the D stage 202 include reserved instruction exceptions and odd address jump traps during pre-branch. Further, various ETs transferred from the IP stage 201 are encoded into step codes and transferred to the A stage 203.

(3, 2, 3) r operand address calculation stage” operand address calculation stage (to stage) 20
3 is divided into two major processing functions. One is a process in which the second decoder of the instruction decoding unit 102 is used to decode the operation code at a later stage, and the other is a process in which the operand address calculation unit 104 calculates an operand address.

The subsequent decoding process of the operation code is D code 2.
12 as an input, and outputs an R code 214 including register and memory write reservations, microprogram entry addresses, parameters for the microprogram, and the like. Note that the register or memory write reservation is performed by the register write reservation unit 18, but the contents of the register or memory referenced in address calculation may be rewritten by an instruction that precedes it on the pipeline, resulting in incorrect address calculation. This is to prevent

To avoid deadlock, write reservations for registers or memory are made at intervals rather than for each step code.

For reservations for writing to registers and memory, please refer to the patent application filed in 1986.
2-144394.

The operand address calculation process takes the A code 213 as input, and operates the operand address calculation unit 1 according to the A code 213.
04 performs address calculation by combining addition or memory indirect reference, and outputs the calculation result as F code 215. At this time, a conflict check is performed when reading registers and memory during address calculation, and if a conflict is indicated because the preceding instruction has not finished writing to the register or memory, the preceding instruction
Wait until the write process is completed at stage 205. It also checks whether the operand address and the memory indirect reference address fall into the I10 area mapped to memory.

The BIT detected in the A stage 203 includes a reserved instruction exception,
privileged instruction exception, hash access exception, address translation exception,
There is a devasogtrasob due to operand breakpoint hints during memory indirect addressing. If the D code 212 or A code 213 itself indicates that an EIT has occurred, the A stage 203 does not perform address calculation processing on that code, and transfers the EIT to the R code 21.
4 and F code 215.

(3, 2, 4) r Micro ROM Access Stage The operand fetch stage (F stage) 2o4 is also roughly divided into two processes. One is access processing of the micro ROM, and is particularly referred to as the R stage 206.

The other is operand prefetch processing, particularly referred to as OF stage 207. The R stage 206 and the OF stage 207 do not necessarily operate simultaneously, but operate independently depending on whether memory access rights can be acquired or not.

Micro ROM access processing, which is the processing of the R stage 206, is performed on the R code 214 at the next E stage 205.
E code 21 which is the execution control code used for execution in
This is micro ROM access and micro instruction decoding processing to generate 6. When processing for one R code 214 is broken down into two or more microprogram steps, the micro ROM is used in the E stage 205 and the next R code 214 waits for micro ROM access. The micro ROM access to the R nid 214 is performed at the time of execution of the last microinstruction in the previous E stage 205. In the data processing device of the present invention, most basic instructions are executed in one microprogram step, so in reality, the micro ROM access to the R coat 214 is often executed one after the other.

There is no new BIT detected in the R stage 206.

When the R code 214 indicates an instruction processing re-execution type EIT, the microprogram for that old T process is executed, so the R stage 206 uses that R code 214.
Fetch microinstructions according to

If R code 214 indicates an odd address jump trap, R stage 206 conveys it via E code 216. This is for pre-branch and E
In stage 205, if a branch does not occur in the E code 216, the pre-branch is made valid and an odd address jump trap is generated.

(3, 2, 5) "r operand fetch stage" Operand fetch stage (OF stage) 207 is F
Of the above two processes performed in stage 204, operand prefetch processing is performed.

Operand prefetch takes F code 215 as input,
The fetched operand and its address are sent to S code 21.
Output as 7. One F code 215 specifies an operand fetch of 4 hides or less, although it may straddle word boundaries. The F code 215 also includes a designation as to whether or not to access the operand, and the A stage 203
When transferring the operand address itself or the immediate value calculated in , to the E stage 205, operand prefetch is not performed, and the contents of the F code 215 are transferred as the S code 217. If the operand to be prefetched matches the operand to be written by the E stage 205, the operand is not prefetched from the memory but is bypassed. Further, operand prefetch is delayed for the T10 area, and operand fetch is performed after waiting until all preceding instructions are completed.

The HITs detected in the leaf stage 207 include a hash access exception, an address translation exception, and a debug trump using the breakpoint hino1- for operand prefetch. F code 215 is B other than debug playing cards
When it indicates IT, it is transferred to the S code 217 and no operand prefetch is performed. F code 215
When indicates a debug trump, its F code 2
15, performs the same processing as when no EIT is indicated, and also transmits a debug trump to the S code 217.

(3, 2, 6) r Execution stage j Execution stage (E stage) 205 operates with E code 216 and S code 217 as input. This E stage 205 is a stage for executing instructions, and all processing performed in stages before the F stage 204 is preprocessing for the E stage 205. When a jump instruction is executed at E stage 205 or BIT processing is started, the process from IF stage 201 to F stage 2 is performed.
All processes up to 04 are invalidated. E stage 205
is controlled by a microprogram, R code 214
The instructions are executed by executing a series of microprograms starting from the entry address of the microprogram indicated in .

Reading of the micro ROM and execution of micro instructions are performed in a pipelined manner. Therefore, when a branch occurs in a microprogram, one microstep becomes available. In addition, the E stage 205 includes the data calculation section 106
It is also possible to perform pipeline processing of operand store within 4 bytes and execution of the next microinstruction using the store buffer located in the .

In the E stage 205, the write reservation for registers and memory made in the A stage 203 is canceled after the operand is written.

Further, if a conditional branch instruction issues a branch at the E stage 205, the branch prediction for that conditional branch instruction was incorrect, so the branch history is rewritten.

BITs detected in the E stage 205 include hash access exception, address translation exception, debug 1-ramp, odd address jump trap, reserved function exception, illegal operand exception, reserved stack formant exception, divide-by-zero trap, and unconditional trap. , conditional traps, delayed context 1-traps, external interrupts, delayed interrupts, reset interrupts, and system failures.

All BITs detected at E stage 205 are processed, but BITs from IF stage 201 before E stage
BIT detected during stage 204 and reflected in R code 214 or S code 217 is not necessarily E
It does not necessarily mean that it will be processed one by one. IP stage 20] to F stage 204, but the preceding instruction is
All BITs that have not reached the E stage 205 due to a jump instruction being executed at the stage 205 or the like are cancelled. This means that the instruction that caused the BIT was never executed in the first place.

External interrupts and delayed interrupts are executed at E stage 205 at the end of instructions.
is directly accepted, and the necessary processing is executed by the microprogram. Other various EIT processes are performed by microprograms.

(3, 31r State control of each pipeline stage) Each stage of the pipeline has an input launch and an output latch, and basically operates independently from other stages. When the processing is completed, the processing result is transferred from the output latch to the input lunch of the next stage, and when all the input signals necessary for the next processing are available at the input lunch of the own stage, the next processing is started.

In other words, in each stage, all input signals for the next process output from the previous stage are valid, the current processing result is transferred to the input lunch of the next stage, and when the output lunch is empty, the next process starts. Start.

All input signals must be available at the clock timing immediately before each stage starts operating. If the input signals are not ready, the stage is in a waiting state (waiting for input). When transferring from the output latch to the input lunch of the next stage, the input lunch of the next stage must be free, and even if the input lunch of the next stage is not free, the pipeline stage will wait. state (waiting for output). If a necessary memory access right cannot be obtained, a wait is inserted into the memory access being processed, or other pipeline conflicts occur, the processing itself at each stage will be delayed.

(3, 4) ``Register Conflict Check'' In the data processing device of the present invention, malfunctions due to register conflicts are avoided in the following manner.

In the data processing apparatus of the present invention, a 16-bit flag is provided corresponding to each step code including the step code being processed. These 16 bit flags correspond to 16 general-purpose registers, respectively.

In the A stage 203, as a result of calculating the operand address, a write reservation is made for registers that may be rewritten when the process progresses to the execution stage 205.

In one write reservation process, any one general-purpose register, all general-purpose registers, ROR4, SP, SP and FP (
Five types of write reservations can be made for the frame pointer). By the write reservation process, flags corresponding to registers that are capable of writing are set to "1". This flag group is transferred in synchronization with the transfer of the step coat.

When the writing process to the register is completed in the execution stage 205, the flag is cleared to "0".

When referring to a register during address calculation, it is checked whether the flag group for the register to be referred to is set to "0". This processing is register conflict check processing.

If the flag for the register to be referenced is "1", this indicates that the value of the register to be referenced may be rewritten by the processing of the preceding step code, indicating that a conflict has occurred. It will be done. If the flag for the register to be referenced is "0", it is guaranteed that the value of the register to be referenced will not be rewritten by the processing of the preceding step code, and the register can be referenced in address calculation. .

If it is detected that a conflict has occurred regarding a register, the A stage 203 delays the start of processing at this stage until the conflict is resolved.

(3,5) rMULX, DIVX instruction processing”M
The ULX and DIVX instructions are multiple precision operation instructions. FIG. 28 shows the bit assignments of these instructions.

The MULX and DIVX instructions are pipelined in three step codes unless multi-indirect mode is used in addressing mode.

The operation result is the second halfword (33 and 3) in the instruction code.
4) is stored in the register indicated by the two write register designation fields (register and memory if the destination designation is memory).

The flowchart in FIG. 29 shows the processing procedure at stage A 203, which represents the features of the present invention.

In stage A 203, code 212. is necessary for processing within the stage. It is in a standby state until the A code 213 is aligned at the input point, and when both codes are aligned, processing begins.

The register write reservation unit 18 checks for address calculation conflicts, and if a conflict occurs, the process at the A stage 203 is redone. If no conflict occurs (or if it is resolved), the address δ1 is calculated according to the instruction of the A code 213 to generate the F code 215.

On the other hand, the D code 212 is input from the D stage 202, and the second decoder performs instruction decoding processing, and the R code 212 is inputted from the D stage 202.
Generate 4. If register write reservation information is included in the D code 212, the register write reservation unit 18 analyzes it and makes a register write reservation.

R code 214 generated at A stage 203. It is determined whether or not to output the F code 215, and if it is to be output, it is checked whether or not the input slot of the F stage 204 is vacant, and if it is vacant, the R code 2 is sent to the input slot.
14. The F code 215 is transferred and the process ends. If it is determined that the R code 214 or the F code 215 is not output, a signal indicating that the R code 214 or the F code 215 is invalid is output to the next stage, and is not input to the input wire of the F stage 204.

In the following explanation, MIIL is used when using memory as the source and register as the destination.
The processing of the X command will be described. However, it is assumed that the multi-stage indirect mode is not used.

An overview of the processing in each step code is shown below.

First step code: calculates the address of the source operand, fetches the operand from memory, and saves it to the working register.

Second step code: Makes a write reservation for the first register.

Third stave code: Specifies the register of the destination operand, instructs the extended multiplication instruction, and releases the register reservation after the operation is completed.

Regarding the third step code, since we are considering the case where the addressing mode of the destination operand is the register direct mode, it includes reservation of the second write register.

First, the processing related to the first step code will be explained with reference to the flowchart in FIG. 30 (al) showing the processing at each stage.

The D stage 202 processes the first halfword (3
1 and 32) and decode it. Then, the D code 212 and A code 213 indicating the first step code are transferred to the A stage 203. In the A stage 203, the second stage decoding process is performed using the D code 212 as input.
An R code 214 is generated and transferred to the F stage 204.

Further, the address calculation of the source operand is performed according to the instruction of the A code 213, and the address information of the calculation result is transferred to the F stage 204 as the F code 215. The F stage 204 receives the R code 214 as input, reads the microinstruction, decodes the microinstruction, generates the E code 216, and transfers it to the E stage 205. Also,
Fetch the operand according to the instruction of F code 215,
The fetched operand is transferred to the E stage 205 as an S code 217. At the E stage 205, the value of the source operand in the S code 217 is saved in the working register according to the instruction from the E code 216.

Next, the processing related to the second step code will be explained with reference to the flowchart in FIG. 30 (bl) showing the processing at each stage.

The D stage 202 processes the second halfword (3
3 and 34) and decode it. At this time, the D code 212 is transferred to the A stage 203 as the second step code with information on the write reservation of the register (register indicated by field 33). A part of the decoding result is held in the launch circuit 17 in the D stage 202 as an intermediate code 16.

Also, the input side of the addressing mode decoder and the D code 212. A lunch is provided on the input side of the field extraction section for generating the A code 213, and holds information necessary for generating the third stamp code among the operation codes. In the A stage 203, according to the instruction of the transferred D code 212, a write reservation is made to a register that stores the upper digit of the execution result of the extended multiplication instruction (in the case of the DIVX instruction, the remainder of the execution result of the extended division instruction).

At this time, R from A stage 203 to F stage 204
As for the output of the code 214, as a result of decoding by the second decoder, it is determined that it will not be output, and a signal instructing the invalidation of the R code 214 is output to the F stage 204. Don't let it be taken in. Therefore, the second step code is A stage 20
3, it becomes the absorbed form.

Finally, regarding the processing related to the third step code,
The processing at each stage will be explained with reference to the flowchart shown in FIG. 30 FC+.

In the D stage 202, the instruction code 211 is not fetched from the IF stage 201, but the intermediate code 16 held in the latch 17 is decoded, the addressing mode decoder is also decoded using the contents of the latch, and each field is also extracted. Processing is performed using the contents of the latch to generate a D code 212 and an A code 213 indicating the third step code, and transfer them to the A stage 203. A stage 20
3, the D code 212 is input and a second stage decoding process is performed to generate an R code 214 having destination register designation information and transfer it to the F stage 204.

Furthermore, in the A stage 203, a write reservation is made to a register that stores the lower digit of the extended multiplication instruction execution result (in the case of the DIVX instruction, the quotient of the extended division instruction execution result).

The F stage 204 receives the R code 214 as input, reads the microinstruction, decodes the microinstruction, and executes E.
A code 226 is generated and transferred to the E stage 205.

E stage 205 executes an extended multiplication instruction according to instructions from E code 216. The results of the operation are stored in the two registers specified by the destination, and the write reservation of the registers is released.

The case where the addressing mode of the destination operand is the register direct mode has been described above.

On the other hand, if the operand is in memory, there is no need to reserve the register write in the third step code, so there is no need to generate the second step code, but it simplifies the processing on the hardware. As in the case of register direct mode, the second . A third step code is also generated. Further, when the multi-stage indirect mode is used, step codes are generated at the D stage 202 for a specified number of stages.

As described above, in the data processing device of the present invention, when there are two general-purpose register specifications for writing in the basic instruction part that is subject to one decoding process, two step codes containing write reservation information for each register are It is generated at stage 202, and a write reservation for each register is made at stage A 203. Also, in A stage 203, E stage 20
In order to reduce the number of step codes processed in Step 5, step codes that only perform reservations are absorbed and are not output as step codes. This occurs when the E stage 205 performs long processing for one step code (
? 1tlL etc.) is effective.

[Results of the Invention] As explained in 4-2 below, according to the data processing device of the present invention, two write register specifications are specified in an instruction code that is a single instruction decoding processing unit, such as a multiple-precision operation instruction. If a field is included, the two register write reservation processes are executed as separate pipeline processing units by dividing them into step codes that include each register specification field, so the decoder for register reservation is divided into two step codes. This has the effect of reducing hardware in that there is no need to provide one. Furthermore, since the step code that only makes register write reservations in the operand address calculation stage is absorbed, the number of step codes processed in the execution stage is reduced. This reduces the time that the step code occupies the execution stage, thus speeding up data processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a pipeline processing mechanism of a data processing device to which the present invention is applied, FIG. 2 is a block diagram showing the configuration of the data processing device of the present invention, and FIGS.
FIG. 7 is a schematic diagram showing the instruction format of the data processing device of the present invention, FIG. 28 is a schematic diagram showing the instruction bit allocation of MULX and DIVX instructions, FIG. 29 is a flowchart showing the operation procedure of the A stage, and FIG. 30 31 is a flowchart showing the processing at each stage of each step code in the execution of a multiple-length arithmetic instruction, and FIG. 31 is a block diagram showing the configuration of a conventional pipeline processing mechanism. 15...Decoder 16...Intermediate code 18
...Register write reservation section 102...Instruction decoding section 104...Operand address calculation section 106.
...Data calculation unit 202...Instruction decode stage 203...Operand address calculation stage 20
5... Instruction execution stage Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a data processing device equipped with a mechanism for pipeline processing of instructions through a plurality of stages including an instruction decode stage for decoding the instructions, the instruction decode stage includes a first stage for writing operands. an instruction having first and second register specification fields, a first unit processing code including information in the first register specification field, and a second unit processing code including information in the second register specification field. What is claimed is: 1. A data processing device characterized by comprising means for decoding. 2. In a data processing device equipped with a mechanism for pipeline processing of instructions through a plurality of stages including an instruction decode stage for decoding instructions, an operand address calculation stage for calculating operand addresses, and an instruction execution stage for executing instructions. , making a register write reservation for prohibiting a register that is controlled in the operand address calculation stage and that may be rewritten during instruction execution in the instruction execution stage from being referenced during address calculation in the operand address calculation stage. register write reservation means; and a plurality of pre-stage units controlled by the instruction decode stage and including a first pre-stage unit processing code and a second pre-stage unit processing code containing instruction information for one instruction to the register write reservation means. decoding means for decoding into a processing code; and means controlled by the operand address calculation stage for processing the first pre-stage unit processing code and the second pre-stage unit processing code to output one post-stage unit processing code. A data processing device comprising: