JPH0218624B2 - - Google Patents

Info

Publication number: JPH0218624B2
Authority: JP; Japan
Prior art keywords: circuit; output; pulse; signal; flip
Prior art date: 1983-03-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

JP58045314A

Other languages

English (en)

Japanese (ja)

Other versions

JPS59172871A (ja

Inventor

Eiichi Kobayashi

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Corp

Original Assignee

Nippon Electric Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1983-03-19

Filing date

1983-03-19

Publication date

1990-04-26

1983-03-19 Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd

1983-03-19 Priority to JP58045314A priority Critical patent/JPS59172871A/ja

1984-09-29 Publication of JPS59172871A publication Critical patent/JPS59172871A/ja

1990-04-26 Publication of JPH0218624B2 publication Critical patent/JPH0218624B2/ja

Status Granted legal-status Critical Current

Links

238000001514 detection method Methods 0.000 claims description 24
230000005540 biological transmission Effects 0.000 claims description 13
238000000926 separation method Methods 0.000 claims description 4
230000001360 synchronised effect Effects 0.000 claims description 4
238000006243 chemical reaction Methods 0.000 description 6
238000010586 diagram Methods 0.000 description 4
238000000034 method Methods 0.000 description 2
230000002123 temporal effect Effects 0.000 description 2
230000003111 delayed effect Effects 0.000 description 1
230000000694 effects Effects 0.000 description 1
230000005764 inhibitory process Effects 0.000 description 1
230000000630 rising effect Effects 0.000 description 1

Classifications

- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Landscapes

Engineering & Computer Science (AREA)
Computer Networks & Wireless Communication (AREA)
Signal Processing (AREA)
Time-Division Multiplex Systems (AREA)
Dc Digital Transmission (AREA)
Synchronisation In Digital Transmission Systems (AREA)

JP58045314A 1983-03-19 1983-03-19 受信用多チヤネル分離装置に適用されるチヤネル同期回路 Granted JPS59172871A (ja)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
JP58045314A JPS59172871A (ja)	1983-03-19	1983-03-19	受信用多チヤネル分離装置に適用されるチヤネル同期回路

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP58045314A JPS59172871A (ja)	1983-03-19	1983-03-19	受信用多チヤネル分離装置に適用されるチヤネル同期回路

Publications (2)

Publication Number	Publication Date
JPS59172871A JPS59172871A (ja)	1984-09-29
JPH0218624B2 true JPH0218624B2 (de)	1990-04-26

Family

ID=12715839

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP58045314A Granted JPS59172871A (ja)	1983-03-19	1983-03-19	受信用多チヤネル分離装置に適用されるチヤネル同期回路

Country Status (1)

Country	Link
JP (1)	JPS59172871A (de)

1983
- 1983-03-19 JP JP58045314A patent/JPS59172871A/ja active Granted

Also Published As

Publication number	Publication date
JPS59172871A (ja)	1984-09-29

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