JPH02190349A - Abnormality detection circuit - Google Patents

Abstract

PURPOSE:To remove a detection error due to dispersion of temperature and components and besides, to enable a circuit to be integrated on a gate array by a method wherein an abnormality detection circuit is equipped with a load electrification detection circuit, a clock selection and mode setting circuit, and an up-down counter. CONSTITUTION:A load electrification detection circuit outputs a load electrification signal of a specific value when a current flows to a load, and outputs the load electrification signal of another specific value when no current flows. A clock selection and mode setting circuit supply a second clock signal CK2 to an up-down counter and establishes a motion mode of the up-down counter at an up-counter mode when the load electrification signal is of a specific value, and supplies a first clock signal CK1 to the up-down counter and establishes the motion mode of the up-down counter at a down counter mode when the load electrification signal is of another specific value. Therefore, since neither resistance nor capacitor are used, a constant detection time is always provided without being influenced from variation in temperature and further, integration can be performed on a gate array or the like.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of an abnormality detection circuit that outputs an abnormality occurrence signal when the energization time of the current flowing through the load exceeds a predetermined value. The purpose is to eliminate detection errors and enable the circuit to be integrated into a gate array.When current is flowing through the load, a load energization signal of a predetermined value is output, and when no current is flowing, a load energization signal of a predetermined value is output. a load energization detection circuit that outputs a load energization signal of a value, an up/down counter, and a second clock signal C when the load energization signal is a predetermined value.
K2 is supplied to the up-down counter, the operation mode of the up-down counter is set to up-counter mode, and when the load energization signal is at another predetermined value, the first clock signal CKI is turned up and down. The clock selection and mode setting circuit supplies the clock to the down counter and sets the operation mode of the up/down counter to the down counter mode.

[Industrial application field]

The present invention relates to an improvement in an abnormality detection circuit that outputs an abnormality occurrence signal when the energization time of a current flowing through a load is longer than a predetermined value.

[Conventional technology]

FIG. 8 is an electrical circuit diagram of a conventional abnormality detection circuit. In the figure, l is a solenoid, 2 is a transistor, 3 is a diode, 4 is a light emitting element, 5 is a light receiving element, 6 is an inverting circuit, 7 is a comparator, 8 to 14 are resistors, 15 is a capacitor, and 16 is a diode. It shows.

Solenoid 1 is located inside the print head,
When current flows through solenoid 1, the printing pin hits the paper surface.
When the transistor 2 is turned on, a current flows through the solenoid 1, and at the same time, current flows through the light emitting element 4, the resistor 8, and the diode 3.

The light emitting element 4 and the light receiving element 5 constitute a photocoupler. The light from the light emitting element 4 is received by the light receiving element 5. When light is received, the light-receiving element 5 becomes conductive, *Load energization (g
The number will be low level. *The load energization signal is inverted by the inverting circuit 6. When the output of the 0 inverting circuit 6 reaches a high level, charging of the capacitor 15 is started. The voltage of the capacitor 15 is applied to one terminal of the comparator 7,
A reference voltage is applied to the child terminal of the comparator 7. The comparator 7 outputs a low level when the voltage at one terminal is higher than the voltage at the child terminal. A low level comparator output indicates that an abnormality has occurred. When an abnormality occurs, actions such as turning off the power are performed.

(Problem to be Solved by the Invention) The circuit shown in Fig. 8 detects when the load is energized for longer than specified and notifies the user of an abnormal condition. The disadvantage is that detection errors occur due to variations.

Furthermore, since the circuit shown in FIG. 8 uses resistors and capacitors, it has the disadvantage that it cannot be integrated.

The present invention was created in view of this point, and eliminates detection errors due to variations in temperature and component parts in an abnormality detection circuit that notifies the occurrence of an abnormality when the load energization time exceeds a predetermined time. It also aims to enable the integration of circuits into gate arrays.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. The abnormality detection circuit of the present invention includes a load energization detection circuit, a clock selection and mode setting circuit, and an up/down counter. The load energization detection circuit outputs a load energization signal of a predetermined value when current is flowing through the load, and outputs a load energization signal of another predetermined value when no current is flowing. The clock selection and mode setting circuit supplies the second clock signal CK2 to the up-down counter when the load energization signal is a predetermined value, and sets the operation mode of the up-down counter to up-counter mode. However, when the load energization signal is another predetermined value, the first clock signal CK
Supply I to the up/down counter and change the operation mode of the up/down counter to the down counter.
Set to mode.

〔Example〕

FIG. 2 is a block diagram of one embodiment of the present invention.

In the figure, 21 and 22 are up/down counters, 23 is a comparison circuit, 24 to 27 are D flip-flops, 28 and 29 are AND gates, 30 is an OR gate,
Reference numeral 31 indicates an inverting circuit.

A to D of the counter 21 are data input terminals, CK is a clock terminal, LOAD is a load terminal, UP/DOWN is an up/down terminal, G is an enable terminal, QA or QD is a data output terminal, and RIPPLE is a count value that is all 1. The terminals that output low-level signals when The counter 22 has the same configuration as the counter 21. The RIPPLE terminal of the counter 21 is connected to the G terminal of the counter 22. Comparison circuit 23
PO through P7 represent data input terminals, and QO through Q7 also represent data input terminals, respectively. When P=Q, the comparison circuit 23 outputs a low level from the P-Q terminal.

A clock signal CKI is applied to the clock terminal of the D flip-flop 24, and the Q output is connected to the D input. The Q output becomes the clock signal CK2. Therefore, the frequency of clock signal CK2 is 1/1 of clock signal CKI.
It becomes 2. Clock CK2 is applied to the clock terminal of the D flip-flop 25, and the D flip-flop is applied to the D input.
The Q output of flop 26 is applied. D flip
The Q output of the flop 25 is applied to a first input of an AND gate 28 and also applied to a first input of an AND gate 29 via an inverting circuit 31 . D flip flop 2
A *load energization signal is applied to the D input of No. 6, and an inverted version of the clock signal CK1 is applied to the clock terminal. The Q output of D flip-flop 26 is applied to the D input of D flip-flop 25 and to the UP/DOWN terminals of counter 21.22.

An initial reset signal iR3 is applied to the D input of the D flip-flop 27, an initial reset signal iR8 is applied to the CLR terminal, and a clock signal CK is applied to the clock terminal.
I is applied. The Q output of D flip-flop 27 is applied to the LOAD terminal of counter 21.22. The initial reset signal iR3 is a signal that becomes high level when the power is turned on.

The Q output of the D flip-flop 25 is applied to the first input of the AND gate 28, and the clock signal C is applied to the second input of the AND gate 28.
KI is applied, and the signal of the P-Q terminal of the comparator circuit 23 is applied to the third human power.

The first input of the AND gate 29 is applied with the inverted Q output of the D flip-flop 25, the second input is applied with the clock signal CK2, and the third input is applied with the RIPPLE output of the counter 22. has been done. The output of the AND gate 28 is applied to the first input of the OR gate 30, and the output of the AND gate 29 is applied to the second input of the OR gate 30. The output of the OR gate 30 is applied to the clock terminals of the counters 21 and 22.

The operation of the embodiment shown in FIG. 2 will be explained. When the initial reset signal iR8 goes high, the counters 21 and 22 are initialized. In the illustrated example, the counter 21 is
, 22 are set to X"7F". *When the load energization signal is at a high level, the clock signal CKI is output from the OR gate 30, and the counters 21 and 22 operate as down counters. counter 21.22
When the count value of is X"7F", P=Q of the comparison circuit 23
A low level is output from the terminal, and the supply of clock signals to the counters 21 and 22 is stopped.

*When the load energization signal becomes low level, counter 21.2
2 operates as an up counter, and a clock signal CK2 is output from the OR gate 30. counter 2
When the count values of 1 and 22 reach X″FF1, the counter 22
A low level is output from the RIPPLE terminal of , and the supply of clock signals to counters 21 and 22 is stopped.

The signal of the RIPPIJQ child is sent to a monitoring device (not shown), and when this signal goes to a low level, power is cut off, etc.

FIG. 3 is a diagram showing the operation at initial setting. When the initial reset signal LR3 becomes high level, the counters 21 and 22
A high level is applied to the LOAD terminal of the counter 21,
Initialization data is set in 22.

FIG. 4 is a diagram showing the operation when the counter changes from up to down operation. When the heavy load energization signal goes high, the Q output of the D flip-flop 26 goes high, then the Q output of the D flip-flop 25 goes high, and the clock signal CKI is output from the OR gate 30. Ru.

FIG. 5 is a diagram showing the operation when the counter changes to the up operation after the counter reaches X"7F". *When the load energization signal is at a high level, the counters 21 and 22 operate as down counters. The count values of counters 21 and 22 are X
When it reaches "7F", the supply of clock signals to the counters 21 and 22 is stopped. Under the condition where the count value is X"7F" *When the load energization signal becomes a low level, the Q output of the D flip-flop 26 becomes a low level, and then the Q output of the D flip-flop 25 becomes a low level. When the Q output of D flip-flop 26 goes low, counters 21,22 operate as up counters.

When the Q output of D flip-flop 25 goes low, OR gate 30 outputs clock signal CK2, which is applied to the clock terminals of counters 21 and 22.

FIG. 6 is a diagram showing the operation when the counter reaches X'FF'. When the count values of counters 21 and 22 reach X"FF" while operating as up counters, the signal at the RIPPLE terminal of counter 22 becomes low level, and the clock signal to counters 21 and 22 is no longer supplied. will be stopped.

FIG. 7 is a diagram showing a comparison of operations between the conventional system and the present invention. The first half of the figure shows the case where the load energization time is within the predetermined time,
The second half shows the case where the load energization time is longer than the predetermined time.In the conventional circuit, if the load energization time is within the predetermined time, the comparator output will not go to a low level, and the load energization time will be longer than the predetermined time. Then, the comparator output becomes a low level.In the present invention, when the load energization time exceeds a predetermined time, the signal at the RIPPLE terminal of the counter 22 becomes a low level.

[Effects of the Invention] As described above, the abnormality detection circuit of the present invention does not use resistors or capacitors like conventional circuits, so it is not affected by variations in capacitors or resistance, source voltage fluctuations, and temperature changes. It has the advantage that it always has a constant detection time and can be integrated into a gate array or the like.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a diagram showing the operation at initial setting, and Fig. 4 is a diagram showing the operation at the time of initial setting.
The figure shows the operation when the counter changes from up to down operation, Figure 5 shows the operation when the counter changes to up operation after reaching X"7F", and Figure 6 shows the operation when the counter changes to X9FF. Figure 7 shows the operation when ' is reached.
The figure shows a comparison of the operations of the conventional system and the present invention, and FIG. 8 is an electrical circuit diagram of the conventional abnormality detection circuit. 1...Solenoid, 2...Transistor, 3...
Diode, 4... Light emitting element, 5... Light receiving element, 6
...Inverting circuit, 7...Comparator, 8 to 14
...IIE resistor, 15...capacitor, 16...diode, 21 and 22...up/down counter, 23...comparison circuit, 24 to 27...D flip-flop, 28 and 29...AND gate, 30...
...OR gate, 31...inversion circuit. Patent applicant Patent attorney representing Pfn Co., Ltd.
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Claims (1)

[Scope of Claims] A load energization detection circuit that outputs a load energization signal of a predetermined value when current is flowing through the load, and outputs a load energization signal of another predetermined value when no current is flowing;・A down counter and a second clock signal C when the load energization signal is a predetermined value.
K2 is supplied to the up/down counter, the operation mode of the up/down counter is set to up counter mode, and when the load energization signal is at another predetermined value, the first clock signal CK1 is turned up/down. An abnormality detection circuit comprising a clock selection and mode setting circuit that supplies a clock to a down counter and sets the operating mode of the up/down counter to down counter mode.