JPH02192093A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that can be used effectively even if there is a defective memory element (hereinafter referred to as a "memory cell").

[Conventional technology]

A conventional semiconductor memory device that can be used effectively even if there are defective memory cells is disclosed in Japanese Patent Laid-Open No. 598199.

This semiconductor memory device has n external address signals A.
, A ... A memory cell is selected by 1
2 n storage device. If a defective memory cell exists in this semiconductor memory device, the address where the defective memory cell exists is A([A, A...A,...f 1 2
1 A] = (a, a・a, -anko2
), the potential of the signal electrode of the external address signal A (i=any one of l to n) is fixed to an inverted value of the signal value a. As a result, the possibility that the memory cell at the defective address Ar of this semiconductor memory device will be accessed becomes zero.

Therefore, when using this semiconductor memory device, the external address signal A,
External address signal A -A, -1°A1+1 excluding
It is used as a semiconductor memory device accessible by ~An. As a result, although the storage capacity is reduced by half, this semiconductor memory device can be effectively used as a normal semiconductor memory device without defective memory cells.

In order to fix the potential of the signal electrode of the external address signal A, this semiconductor memory device has a chip 1 as shown in FIG.
Signal electrode 2 for external address signal A within. A power supply electrode 3 and a ground electrode 4 are formed. Then, the signal electrode 2 of the external address signal A is connected to the power supply electrode 3 according to the signal value ai.
Alternatively, the wire 5 is bonded to one of the ground electrodes 4 to fix the potential of the signal electrode 2 of the external address signal A1.

[Problem to be solved by the invention]

A conventional semiconductor memory device that can be used effectively even if there is a defective memory cell is configured as described above, and it is necessary to form at least one signal electrode for an address signal, a ground electrode, and a power supply electrode on the circuit. Ta.

However, each electrode has a diameter of about 200×200[μm
Since it requires an area of about 2], there is a problem in that it impairs circuit integration.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can be used effectively even if there are defective memory cells without impairing integration.

[Means to solve the problem]

A semiconductor memory device according to the present invention includes a plurality of external address signal input terminals, an internal address signal line connected to each of the external address signal input terminals, a first power supply terminal from which a first power supply level is obtained, and a second power supply terminal. first and second power supply terminals provided between at least one of the second power supply terminals from which a power supply level of 2 is obtained; and the first or second power supply terminal and at least one of the internal address signal lines; a power supply line, a first fuse provided on a power supply line connection internal address signal line that is an internal address signal line connected to the first and second power supply lines or on the first power supply line; and the power supply line. a second fuse provided on the connected internal address signal line or the second power supply line, and when the first fuse is cut, the internal address signal line connected to the power supply line is connected to the first and second power supply lines. When the power supply level is fixed at one of the power supply levels and the second fuse is cut off, the power supply line connection internal address signal line becomes
The power level is fixed to the other of the first and second power levels.

[Effect]

In this invention, when the first fuse is cut off, the power supply line connecting internal address 7 signal line is set to one of the first and second power supply levels, and when the second fuse is cut off, Power line connection internal address signal line,
Since the power level is set to the other of the first and second power levels, the first. By selectively cutting off the second fuse, the power line connection internal address signal line can be fixed at the first or second power level.

〔Example〕

FIG. 1 is a circuit diagram showing part of a semiconductor memory device according to a first embodiment of the present invention. Note that this semiconductor memory device has zero external address signal input terminals PA1 to PAn. As shown in the figure, external address signal input terminals P A, (i-1 to n) are connected to internal address signal lines 13
It is connected to the. Power supply lines 16 and 17 are connected to the node N1 on this internal address signal line 13, respectively.

The power supply line 16 is connected to the power supply V via the fuse element 11 and the resistor R1 connected in series. 0, and the power supply line 17 is grounded via the fuse element 12 and resistor R2 connected in series. The fuse elements 11 and 12 are made of polysilicon or the like and can be cut by heating.

Further, the internal address signal line 13 is connected to the address buffer 10.
This address buffer 10 receives an internal address signal S based on the potential level of the internal address signal line 13.
, , outputs an internal address inversion signal S.

In such a configuration, the address A' ([A, A . . . A, . . . f
L2l...a,...a/] An]2-[al, a2□.

Consider the case in which a defect in the memory cell (2) is detected during the manufacturing process. Note that in this specification, the potential of the internal address signal line 13 indicates the input potential to the address buffer 10.

At this time, if the signal value a' of the external address signal A of the address Ar is "H" (vcc), the fuse element 11 is heated and cut by the laser beam during the manufacturing process. As a result, the potential of the internal address signal line 13 becomes "
Since it is fixed at "L" (ground level), the possibility that the memory cell with the defective address Ar will be accessed becomes zero. On the other hand, if the signal value a, / of the external address signal Ai of the address A is rLJ, the fuse element 12 is heated and cut by the laser beam during the manufacturing process.

As a result, the potential of the internal address signal line 13 is fixed to rHJ, so the possibility that the memory cell at the defective address A will be accessed becomes zero.

Therefore, this semiconductor memory device is controlled by the external address signal A.
External address signals A1 to A1-1'A - except for
Semiconductor storage device 1 accessible by A
n Used as a position. As a result, storage capacity is halved, but
This semiconductor memory device can be effectively used as a normal semiconductor memory device without defective memory cells.

In this way, the potential of the internal address signal line 13 is fixed by cutting the fuse elements 11, 12, thereby making effective use of the semiconductor memory device. These fuse elements 11
．． The area required to form the resistor 12 may be about 4×10 [μm 2 ], and the resistors R1 and R2 do not require a separate formation area and can be easily formed under the power supply line or signal line. Therefore, the integration of the semiconductor memory device is not impaired by the formation of the fuse elements 11 and 12 and the resistors R1 and R2.

Note that when there is no defective memory cell (hereinafter referred to as "normal time"), fuse elements 11 and 12 are not cut.

FIG. 2 is a circuit diagram showing part of a semiconductor memory device according to a second embodiment of the invention. As shown in the figure, the first
In addition to the circuit configuration shown in the figure, an inverter 14 and a fuse element 15 are inserted between the external address signal input terminal PA□ and the node N1.

That is, the external address signal input terminal PA1 becomes the input power of the inverter 14, and the output of the inverter 4 and the node N
A fuse element 15 is provided between 1 and 1.

In such a configuration, the address A' ([A, A . . . A.

r l 2 t...An]2-[a1', a2'...al'...
Consider the case where a defect in the memory cell a'(2) is detected during the manufacturing process.

At this time, if the signal value a, of the external address signal A of the address Ar is rHJ (Voo), the fuse elements 11 and 15 are heated and cut by the laser beam during the l manufacturing process. As a result, the potential of the internal address signal line 13 is fixed at "L" (ground level), so the possibility that the mesori cell with the defective address A' will be accessed becomes zero.

On the other hand, the signal value a of the external address signal A1 of address A,
, / is rLJ, fuse elements 12 and 15 are heated and cut by a laser beam during the manufacturing process. As a result, the potential of the internal address signal line 13 is fixed to rHJ, so the possibility that the memory cell with the defective address Ar will be accessed becomes zero.

In this way, effective utilization can be achieved in the same way as the semiconductor memory device of the first embodiment.

Note that it is the inverter 4 that cuts the fuse element 15 together with the fuse element 11 or 12.
This is to prevent the influence of unstable output from reaching the internal address signal line 13.

The reason why the output of the inverter 14 becomes unstable is that the input to the inverter 14 becomes unstable because the external address signal input terminal PAt is not used when the potential of the internal address signal line 13 is fixed.

Incidentally, in the semiconductor memory devices shown in the first and second embodiments, an external address signal Ai is naturally inputted to the external address signal input terminal PA1 under normal conditions.

At this time, in the semiconductor memory device of the first embodiment, if the external address signal A is rLJ, the power supply V is applied. If a current flows between 0 and external address signal input terminals PA1, and external address signal A is rHJ, external address signal input terminal P
There is a drawback that current t flows between one ground level.

On the other hand, in the semiconductor memory device of the second embodiment, since an inverter is provided on the internal address signal line 13, normally,
“H” of external address signal A1.

r Regardless of LJ, power supply ■. There is an advantage that no current flows between the C1 external address signal input terminal PAi and between the external address signal input terminal P and the ground level.

t Note that the above-mentioned drawbacks of the semiconductor memory device of the first embodiment can also be solved by cutting both fuse elements 11 and 12 during normal operation. Therefore, the semiconductor memory device of the second embodiment is effective when both fuse elements 11 and 12 are not disconnected during normal operation.

FIG. 3 is a circuit diagram showing a semiconductor memory device according to a third embodiment of the invention. As shown in the figure, an inverter 18 . Fuse element 19. Inverter 20. The fuse element 21 is inserted in this order.

Fuse element 19. The power supply line 22 is connected to the node N2 on the internal address signal line 13 between the inverters 20, and the fuse element 21. Power line 2 is connected to node N3 between address buffers 10.
3 are connected to each other.

The power line 22 is grounded via a resistor R3, and the power line 23 is grounded via a resistor R4.

That is, in this embodiment, both power supply lines 22 and 23 are grounded, and fuse elements 19 and 21 are provided on the internal address signal line 13.

Other configurations include 1. Since it is the same as the second embodiment, the explanation will be omitted.

Even with this configuration, the potential of the internal address signal line 13 can be fixed at rHJ by cutting the fuse element 19, and the potential of the internal address signal line 13 can be fixed by cutting the fuse element 21. Since it can be fixed to rLJ, the first. The same effects as the second embodiment are achieved.

Also, as in the second embodiment, since an inverter is provided on the internal address signal line 13, the external address signal input terminal P and the ground level i are normally maintained regardless of rHJ and rLJ of the external address signal A. This has the advantage that no current flows between them.

In addition, the power supply lines 22 and 23 of the third embodiment are connected to resistors R3 and R
Power supply V through 4. A configuration connected to 0 is possible. In this case, by cutting the fuse element 19, the potential of the internal address signal line 13 can be fixed at rLJ, and by cutting the fuse element 21, the potential of the internal address signal line 13 can be fixed at rHJ. Can be done.

In the first to third embodiments described above, the power supply lines (1617, 2
2, 23), resistors (R1, R2°R3, R4) are always inserted above them. These resistors are of course necessary when detecting a defective memory cell, and are necessary during normal times (in the first and second embodiments,
This element is also necessary in the case where the fuse elements 11 and 12 are not cut. In the second embodiment,
If fuse elements 11 and 12 contain a resistance component,
There is no need to separately provide resistors R1 and R2. However, the resistors R3 and R4 provided on the power supply lines 22, 23 in the third embodiment are essential.

Further, in the present invention, at least one internal address signal line may have the configuration shown in FIG. 1, FIG. 2, or FIG.
It is not necessary to use the configuration shown in FIGS. 1, 2, or 3.

Furthermore, the power source V is not limited to the configuration shown in FIGS. 1 to 3. 0 or ground level, a first fuse provided on an internal address signal line connected to the power supply line or on one of the power supply lines, and a first fuse provided on the internal address signal line connected to the power supply line or on one of the power supply lines. and a second fuse provided on the other power supply line, and by cutting the first fuse, the potential of the internal address signal is fixed to one of rHJ and rLJ, and the second fuse is cut. By doing this, the potential of the internal address signal is set to rHJ.
, rLJ can be fixed to the other potential.

〔Effect of the invention〕

As explained above, according to the present invention, when the first fuse is disconnected, the power supply line connection internal address signal line is set to one of the first and second power supply levels, and the second power supply level is set to the second power supply level. When the fuse is cut off, the internal address signal line connected to the power supply line is set to the other of the first and second power supply levels. By selectively cutting off the second fuse, the power line connection internal address signal line can be fixed at the first or second power level. As a result, even if there are defective memory cells, they can be used effectively without impairing integration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a part of a semiconductor memory device according to a first embodiment of the invention, FIG. 2 is a circuit diagram showing a part of a semiconductor memory device according to a second embodiment of the invention, FIG. 3 is a circuit diagram showing a part of a semiconductor memory device according to a third embodiment of the present invention, and FIG. 4 is a schematic plan view showing a conventional semiconductor memory device. In the figure, 11, 12, 15, 19.21 are fuse elements, 13 is an internal address signal line, 14° 18.20 is an inverter, 16, 17.22 23 is a power line, vCC
is the power supply. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A plurality of external address signal input terminals, an internal address signal line connected to each of the external address signal input terminals, a first power supply terminal that obtains a first power supply level, and a first power supply terminal that obtains a second power supply level. a first power supply terminal provided between at least one of the second power supply terminals and at least one of the first or second power supply terminals and at least one of the internal address signal lines.
and a second power supply line, and a first fuse provided on a power supply line connection internal address signal line that is an internal address signal line connected to the first and second power supply lines or on the first power supply line. , on the internal address signal line connected to the power supply line or on the second
a second fuse provided on the power supply line, and when the first fuse is cut, the power supply line connection internal address signal line is set to one of the first and second power supply levels. The semiconductor memory device is characterized in that the internal address signal line connected to the power supply line is fixed to the other one of the first and second power supply levels when the second fuse is blown.