JPH02192111A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To properly conduct exposure corresponding to the thickness of resist in a chip region and a scribe-line region by a method wherein a light-dimming filter is formed on the chip region. CONSTITUTION:A light-dimming filter 2, with which a light transmitting rate is decreased is formed only on a chip region, excluding a scribeline region, on the pattern surface of a glass substrate 1 of reticle or photomask for manufacture of a semiconductor integrated circuit. To be more precise, a metal or metal oxide thin film, with which a light-transmitting rate is decreased, is formed on the chip region of the glass substrate 1 using a vapor deposition or sputtering method, colored glass is coated, the film of the light-dimming filter 2 is formed, and the pattern of the light-dimming filter 2 is formed on the chip region by patterning using a photolithographic technique. As a result, the over-exposure of the chip region can be prevented when a proper exposing operation is conducted on the scribe line by decreasing an incident light, and a proper exposure can be conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a resist pattern using photolithography technology.

A resist film is formed on a semiconductor substrate having a scribe line for the purpose of increasing the exposure amount of the scribe line area relative to the exposure amount of the chip area, and the scribe line area corresponding to the desired pattern film that blocks light is formed. The resist film is constructed by exposing the resist film to light using a photomask having a light-absorbing film provided on the corresponding chip region.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a resist pattern using photolithography technology.

In recent years, multilayer wiring for semiconductor integrated circuits has been moving from two-layer wiring to three-layer wiring as the degree of integration increases.

For this reason, the step difference between the chip area and the scribe line area becomes large, and a large difference occurs in the thickness of the resist between the chip area and the scribe line area in photolithography technology.

It is becoming difficult to obtain a suitable resist pattern.

For this reason, in the photolithography process.

Corresponding to the thickness of the resist in the chip area and the scribe line area, in order to perform proper exposure, it is necessary to increase the exposure amount in the scribe line area compared to the chip area.

[Conventional technology]

FIG. 6 is an explanatory diagram of a conventional example.

In the figure, 14 is a silicon (St) substrate, 15 is a silicon dioxide (SiOz) film, 16 is a first layer aluminum (A n ) wiring film, and 17 is phosphosilicate glass (PSG).
Membrane, 18 to the second layer! The wiring film 19 is a resist.

In the conventional technology, as shown in FIG.

The process of patterning two-layer wiring will be explained as an example.

The first layer A! is applied to the 5in2 film 15 on the Si substrate 14. After forming the wiring film 16, a PSG film 17 is coated as an insulating film between the eyebrows.

Next, after covering the entire surface with the second layer 1-wiring film 18, AI! , the wiring film 18 is patterned, but at this time, at the boundary between the chip region and the scribe line region, due to the difference in level between the two layers of the second layer ^2 wiring film 18, the PSG film 17, and the 5in2 film 15. Second layer A! A large difference occurs in the thickness of the resist 19 on the film 18.

Since the resist 19 is in a liquid state when applied, it tends to be applied almost flat even if there are steps on the underlying surface.For this reason, when exposing the resist, the resist 19 is exposed so that the thickest scribe line area is exposed. As a result, the chip area is overexposed, and the resist 19 that forms wiring in the chip area becomes thinner, making it impossible to form a pattern with appropriate dimensions.

In the process of forming the AJ2 wiring film of the second layer, a step occurs in the scribe line because the 7/2 wiring film 16 of the first layer in the multilayer process and the PSG film 17 of the eyebrow insulating film are etched. If A1 or PSG film is left on the scribe line without doing this, the following problems will occur during scribing.

That is, if 1 is left, Al1 will scatter onto the chip during scribing, causing bonding defects and short circuit defects.

Furthermore, if the PSG film is left behind, a crank will enter during scribing, causing a problem in moisture resistance.

For this reason, conventional methods have taken measures such as shifting the pattern width to be thicker at the time of designing the reticle or mask in advance in order to cope with the thinner wiring.

[Problem to be solved by the invention]

Therefore, as described above, if the exposure is over-exposed, the resist pattern becomes thinner overall, but as shown in FIG.
Cover with the SG film 23, form the second Aj2 wiring film 24 on the entire surface, apply the resist 19 on it, dry it, and proceed to the second layer! When the wiring film 18 is patterned, the first pattern Aj
At the edge position of the second wiring film 22, the first layer A! Wiring film 2
2 steps lead to the second floor! A phenomenon occurs in which the wiring film 24 is recessed and the incident light hitting the recessed surface locally makes the resist pattern thinner due to halation of A It l]I.

In the present invention, the chip area is overexposed.

To prevent the wiring pattern from becoming thin,
The purpose is to propose a method for applying an appropriate amount of exposure to each area.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 1 is a glass substrate of a reticle or photomask, and 2 is a neutral density filter.

As shown in FIG. 1, on the patterned surface of the glass substrate 1 of a reticle or photomask for semiconductor integrated circuit manufacturing, excluding the scribe line area, there is a light reduction method that reduces the transmittance of light. Filter 2 is formed.

That is, by forming a thin film of metal or metal oxide film to reduce the light transmittance on the chip area of the glass substrate 1 by vapor deposition or sputtering, or coating it with dichroic glass,
A film of the neutral density filter 2 is created and patterned by photolithography to form a pattern of the neutral density filter 2 on the chip area.

Then, the intensity of the incident light is lowered to prevent the chip area from being overexposed when the scribe line area is properly exposed.

[Effect]

By forming a dark filter in the chip region, the difference in exposure amount due to the difference in resist thickness between the scribe line region and the chip region can be eliminated, and proper exposure can be performed.

Also, when performing exposure using a reduction exposure device.

By using a narrow band pass filter that only passes the wavelength of the light used in the exposure device, it is possible to reduce the chromatic aberration of the reduction lens, which can be expected to improve resolution.

〔Example〕

Figure 2 shows the resist thickness in the chip area and scribe line area, Figure 3 shows the change in light intensity when using a neutral density filter, and Figure 4 shows the relationship between chromium (Cr) film thickness and light transmittance.
FIG. 5 shows a schematic sectional view of an embodiment of the present invention.

In the figure, 3 is a Si substrate, 4 is a PSG film and SiO□
5 is an Affi wiring film, 6 is a resist, 7 is a reticle, 8 is a Cr mask pattern, 9 is a Cr film as a light absorbing film, 10 is a Si substrate, 11 is a 5i02 film, 12
2 is a film, and 13 is a resist.

In the embodiment, a case will be described in which a four-chip reticle is used in a reduction projection exposure apparatus.

The reason for using a 4-chip reticle is: (1) In the case of a chip reticle, when stepwise exposure is performed, the scribe line area overlaps and is exposed, resulting in double exposure, and the exposure is appropriate for the thickness of the film. This is because it is not effective.

As shown in FIG. 2, when comparing the difference in resist thickness due to the step difference between the PSG film 4 and A on the Si substrate 3 and the single wiring film 5, it is found that the resist thickness a in the chip area is equal to the scribe line. In the case where the thickness of the resist in the region is 1/2, a neutral density filter is required whose light attenuation amount is 50χ.

FIG. 3 shows an example of changes in light intensity when using a neutral density filter.

When using a Cr film as a neutral density filter.

As shown in Figure 4, the light transmittance of Cr can be cut by 100% with a thickness of 200 mm, and can be reduced to 50% with a thickness of 100 mm, so it is necessary as a neutral density filter. The thickness of the Cr film is 100 mm.

As shown in FIG. 5, a pure Cr film 9 is deposited on the surface of the Cr mask pattern 8 of the reticle 7 by sputtering at a vacuum level of 5xlO.
-3Torr, acceleration voltage 200■, Ar
Coat to a thickness of 100 mm in a gas atmosphere.

Next, this Cr film 9 is removed by etching except for the chip area using photolithography.

The reticle 7 on which the Cr film 9 as a neutral density filter is formed on the chip area is mounted on a reduction projection exposure device, and the reticle pattern is projected and exposed onto the resist lines 3 on the Si substrate 10 to properly expose the entire surface of the St substrate 10. A pattern of the resist 13 for patterning the l-wiring film 12 could be obtained.

Note that the chip area pattern of the neutral density filter on the reticle is large, measuring several mm square, and the tolerance for pattern dimensions is large. Therefore, colored SOG may be applied to the glass surface and the scribe line area removed by etching after firing. , it is also possible to paste a color film for artwork.

〔Effect of the invention〕

Conventionally, the pattern dimensions were corrected in anticipation of the thinning of i-wiring patterns on reticles and photomasks, but as miniaturization progresses in the future, it will become impossible to make corrections, and the present invention will be further improved. be effective.

Furthermore, when using a reduction exposure device, it is also possible to use a narrow band pass filter to reduce dichromatic aberration and improve resolution.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. Figure 2 shows the thickness of the resist in the chip area and scribe line area. Figure 3 shows the change in light intensity when using a neutral density filter. Figure 4 shows the relationship between Cr film thickness and light transmittance. FIG. 5 is a schematic sectional view of one embodiment of the present invention. FIG. 6 is a schematic diagram of a scribe line area in a conventional example. FIG. 7 is a schematic cross-sectional view and a plan view showing the influence of a wiring layer pattern on a second layer due to an edge of a wiring film on a first layer in a conventional example. In fig. 1 is a glass substrate, 2 is a neutral density filter 3 is a Si substrate, and 4 is a PSG film and a 5iO7 film. 5 ha! Wiring film, 6 is resist. 7 is a reticle and 8 is a Cr mask pattern. 9 is a Cr film, and 10 is a Si substrate. 11 is 5i02 film, 12 is AI! , wiring membrane. 13 is resist-9c sister ρC consultation needle V east ``acy>) Hama 1 Noro M6 Goshima Danki Elle 1
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Claims (1)

[Claims] A photomask having a resist film formed on a semiconductor substrate having a scribe line, and having a light absorbing film provided on a corresponding chip area except for the scribe line area corresponding to a desired pattern film that blocks light. A method for manufacturing a semiconductor device, comprising: exposing the resist film to light.