JPH02192145A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02192145A
JPH02192145A JP1124289A JP1124289A JPH02192145A JP H02192145 A JPH02192145 A JP H02192145A JP 1124289 A JP1124289 A JP 1124289A JP 1124289 A JP1124289 A JP 1124289A JP H02192145 A JPH02192145 A JP H02192145A
Authority
JP
Japan
Prior art keywords
fuse
wiring
insulating film
area
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1124289A
Other languages
Japanese (ja)
Inventor
Kazuhiro Suzuki
鈴木 一寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1124289A priority Critical patent/JPH02192145A/en
Publication of JPH02192145A publication Critical patent/JPH02192145A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To make small the area to be occupied by a fuse formation part in a chip and, moreover, to prevent the insulation failure, which is caused by breaking, of an interlayer insulating film and a field insulating film by a method wherein a fuse consisting of a poly silicon wiring is provided between first and second Al wiring layers. CONSTITUTION:A fuse consisting of a poly silicon wiring 3 is forned on a first Al wiring 2 formed on an interlayer insulating film 4 and is connected to a second Al wiring 1 formed on the film 4. Thereby, the area of a fuse formation part becomes equal with the areas of the wirings 2 and 1 formed somewhat wider than the wiring 3 and can be made smaller than the area of that formed by a conventional method. Moreover, as the fuse is formed in such a way that it is pinched by the wirings 2 and 1 in the direction over a semiconductor substrate 6, the insulation failure, which is caused by breaking, of the upper and lower parts of the fuse can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ヒユーズ内蔵型半導体装置に関し、特に第1
アルミ配線層と第2アルミ配線層間に形成する、多結晶
シリコン配線からなるヒユーズの構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device with a built-in fuse, and particularly to a first semiconductor device.
The present invention relates to the structure of a fuse made of polycrystalline silicon wiring formed between an aluminum wiring layer and a second aluminum wiring layer.

〔従来の技術〕[Conventional technology]

従来、内部の抵抗などをトリミングするためのヒユーズ
や冗長回路を内蔵したヒユーズ内蔵型半導体装置は、多
結晶シリコン配線からなるヒュズを第1アルミ配線間に
設け、さらに熱による破壊を防ぐため、ヒユーズ上部の
層間絶縁膜、及びパッシベーション膜を、一部除いて窓
を設けた構造となっていた。
Conventionally, semiconductor devices with built-in fuses, which have built-in fuses and redundant circuits for trimming internal resistance, etc., have a fuse made of polycrystalline silicon wiring between the first aluminum wirings, and a fuse made of polycrystalline silicon wiring to prevent damage due to heat. It had a structure in which a window was provided by removing a portion of the upper interlayer insulating film and passivation film.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のヒユーズ内蔵型半導体装置は、第2図(
a)、(b)に示すように、フィールド絶縁膜5上に多
結晶シリコン配線3からなるヒユーズを第1アルミ配線
2間に設け、コンタクト7を介して接続している、さら
に熱による破壊を防ぐため、ヒユーズ上部の層巻絶縁膜
4及びパッシベーション膜9を一部除いて窓8を設けた
構造となっている。この構造では、ヒユーズを形成して
いる部分の第1アルミ配線2間、第1アルミ配線2と窓
8間の距離を離す必要がある。さらにコンタクト7が必
要なため、チップ内における面積の制圧が大きくなると
いう欠点が有る。
The conventional fuse built-in semiconductor device described above is shown in FIG.
As shown in a) and (b), a fuse consisting of a polycrystalline silicon wiring 3 is provided on a field insulating film 5 between the first aluminum wirings 2 and connected via a contact 7. In order to prevent this, the layered insulating film 4 and passivation film 9 above the fuse are partially removed and a window 8 is provided. In this structure, it is necessary to increase the distance between the first aluminum wires 2 in the portions forming the fuse and between the first aluminum wires 2 and the window 8. Furthermore, since the contact 7 is required, there is a drawback that the area within the chip is increased.

さらに、窓8は層間絶縁膜4の破壊を防ぐ効果は有るが
フィールド絶縁5の破壊による絶縁不良を防止できない
という欠点が有る。
Further, although the window 8 has the effect of preventing breakdown of the interlayer insulating film 4, it has the disadvantage that it cannot prevent insulation failure due to breakdown of the field insulation 5.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のヒユーズ内蔵型半導体装置は、半導体基板の一
主面上に形成された第1アルミ配線層と、第2アルミ配
線層間に、多結晶シリコン配線からなる電流で溶断する
ヒユーズを設けた構造を有している。
A semiconductor device with a built-in fuse of the present invention has a structure in which a fuse made of polycrystalline silicon wiring and blown by a current is provided between a first aluminum wiring layer and a second aluminum wiring layer formed on one main surface of a semiconductor substrate. have.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)は、本発明の一実施例の平面図、第1図(
b)は、第1図(a)のA−A’線断面図である。多結
晶シリコン配線3からなるヒユーズは、層間絶縁膜4上
に形成された、第1アルミ配線2上に形成し、層間絶縁
膜4上に形成された、第2アルミ配線1に接続する。し
たがってヒユーズ形成部の面積は、多結晶シリコン配線
3よりもやや広く形成した、第1アルミ配線2.第2ア
ルミ配線1の面積となり従来より小さくできる。さらに
半導体基板上方向にヒユーズを第1アルミ配線2と第2
アルミ配線1がはさむように形成しているため、ヒユー
ズ上、下部の破壊による絶縁不良を防止することができ
る。
FIG. 1(a) is a plan view of one embodiment of the present invention, FIG.
b) is a sectional view taken along line AA' in FIG. 1(a). A fuse made of polycrystalline silicon interconnect 3 is formed on first aluminum interconnect 2 formed on interlayer insulating film 4 and connected to second aluminum interconnect 1 formed on interlayer insulating film 4 . Therefore, the area of the fuse forming portion is the first aluminum wiring 2. which is formed slightly wider than the polycrystalline silicon wiring 3. The area of the second aluminum wiring 1 can be made smaller than the conventional one. Furthermore, a fuse is connected to the first aluminum wiring 2 and the second aluminum wiring in the upper direction of the semiconductor substrate.
Since the aluminum wiring 1 is formed so as to be sandwiched therebetween, it is possible to prevent insulation failure due to breakdown of the upper and lower portions of the fuse.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、第1アルミ配線層と第2
アルミ配線層間に、多結晶シリコン配線からなるヒユー
ズを設けることにより、ヒユーズ形成部分のチップ内に
しめる面積を小さくでき、かつ層間絶縁膜やフィールド
絶縁膜の破壊による絶縁不良を防止できる効果がある。
As explained above, the present invention provides a first aluminum wiring layer and a second aluminum wiring layer.
By providing a fuse made of polycrystalline silicon wiring between the aluminum wiring layers, it is possible to reduce the area where the fuse is formed within the chip, and also to prevent insulation failure due to breakdown of the interlayer insulation film or field insulation film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は、本発明の一実施例を示す半導体チップ
の平面図、第1図(b)は、第1図(a)のA−A′線
断面図、第2図(a)は、従来例を示す半導体チップの
平面図、第2図(b)は、第2図(a)のA−A’断面
図である。 1・・・・・・第2アルミ配線、2・・印・第1アルミ
配線、3・・・・・・多結晶シリコン配線、4・・・・
・・層間絶縁膜、5・・・・・・フィールド絶縁膜、6
・・・・・・半導体基板、7・・・・・・コンタクト、
8・・・・・・窓、9・・・・・・パッシベーション膜
。 代理人 弁理士  内 原   晋 \
FIG. 1(a) is a plan view of a semiconductor chip showing an embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A' in FIG. 1(a), and FIG. ) is a plan view of a conventional semiconductor chip, and FIG. 2(b) is a sectional view taken along line AA' in FIG. 2(a). 1... Second aluminum wiring, 2... Marked first aluminum wiring, 3... Polycrystalline silicon wiring, 4...
...Interlayer insulating film, 5...Field insulating film, 6
... Semiconductor substrate, 7 ... Contact,
8... Window, 9... Passivation film. Agent Patent Attorney Susumu Uchihara\

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一主面上に形成された第1アルミ配線層と
第2アルミ配線層間に、設けられた多結晶シリコン配線
からなる電流で溶断するヒューズを有することを特徴と
する半導体装置。
1. A semiconductor device comprising a fuse made of polycrystalline silicon wiring provided between a first aluminum wiring layer and a second aluminum wiring layer formed on one principal surface of a semiconductor substrate and blown by current.
JP1124289A 1989-01-19 1989-01-19 Semiconductor device Pending JPH02192145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1124289A JPH02192145A (en) 1989-01-19 1989-01-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1124289A JPH02192145A (en) 1989-01-19 1989-01-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02192145A true JPH02192145A (en) 1990-07-27

Family

ID=11772466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1124289A Pending JPH02192145A (en) 1989-01-19 1989-01-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02192145A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353311A (en) * 2001-05-24 2002-12-06 Nec Corp Semiconductor device and fuse cutting method
JP2007081152A (en) * 2005-09-14 2007-03-29 Renesas Technology Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353311A (en) * 2001-05-24 2002-12-06 Nec Corp Semiconductor device and fuse cutting method
JP2007081152A (en) * 2005-09-14 2007-03-29 Renesas Technology Corp Semiconductor device

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