JPH02192166A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02192166A
JPH02192166A JP1009957A JP995789A JPH02192166A JP H02192166 A JPH02192166 A JP H02192166A JP 1009957 A JP1009957 A JP 1009957A JP 995789 A JP995789 A JP 995789A JP H02192166 A JPH02192166 A JP H02192166A
Authority
JP
Japan
Prior art keywords
amorphous silicon
film
pixel
layer
pixel electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1009957A
Other languages
Japanese (ja)
Inventor
Narimoto Ri
李 成元
Shinji Miyagaki
真治 宮垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1009957A priority Critical patent/JPH02192166A/en
Publication of JPH02192166A publication Critical patent/JPH02192166A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To protect an amorphous silicon film which grows on a lower electrode against cracks by a method wherein the lower electrode which serves as a pixel electrode is separated corresponding to pixels, and amorphous silicon is made to grow thereon. CONSTITUTION:A wiring section is formed of a WSi film 17, and a PSG film 18 is deposited as a flattening layer. Pixel electrodes are formed on the PSG film 18 through sputtering. Then, resist is applied and a specified pixel pattern is formed through a standard technique, and Ar ions are implanted through an ion implantation method using the formed pixel pattern of resist as a mask. A part 26 where Ar ions have been implanted becomes an insulating layer. Next, the resist is removed and an amorphous silicon layer 20 is formed, and a process follows, where ITO is deposited through sputtering for the formation of a transparent electrode 21. By this setup, steps are prevented from being formed on the surface of a semiconductor device of this design and cracks are also prevented from occurring in it.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造方法、特に積層型固体撮像素子に用い
られているアモルファスシリコンの下部電極の形成方法
に関し、 画素電極となる下部電極(導電膜)を個々の画素に対応
して分離しその上にアモルファスシリコンを成長するに
おいて、下部電極の上に成長するアモルファスシリコン
膜にクラックが発生することを防止する方法を提供する
ことを目的とし、 画素電極の上にアモルファスシリコン層を成長させる工
程を含む固体撮像素子の製造において、酸化物超伝導膜
にて画素電極(19a)を形成し、該画素電極(19a
)に画素に対応してイオン注入法によって絶縁層を形成
することを特徴とする半導体装置の製造方法を含み構成
する。
[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a method for forming a lower electrode of amorphous silicon used in a stacked solid-state image sensor, the lower electrode (conductive film) that becomes a pixel electrode is formed into individual layers. The purpose of this invention is to provide a method for preventing cracks from occurring in the amorphous silicon film grown on the lower electrode when separating it corresponding to the pixel and growing amorphous silicon on it. In manufacturing a solid-state imaging device including a step of growing an amorphous silicon layer, a pixel electrode (19a) is formed from an oxide superconducting film, and the pixel electrode (19a) is
) includes a method for manufacturing a semiconductor device, characterized in that an insulating layer is formed by an ion implantation method corresponding to a pixel.

〔産業上の利用分解〕[Industrial use decomposition]

本発明は半導体装置の製造方法、特に積層型固体撮像素
子に用いられているアモルファスシリコンの下部電極の
形成方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a lower electrode of amorphous silicon used in a stacked solid-state image sensor.

〔従来の技術] 近年、撮像素子において、光応答が早く、かつ、画質欠
陥のない高品質な素子が要求されている。それには、電
極の抵抗が低いことと、欠陥のない均一なアモルファス
シリコン膜を成長することとが要求されている。
[Prior Art] In recent years, there has been a demand for high-quality image pickup devices that have a fast photoresponse and are free from image quality defects. This requires low electrode resistance and the growth of a uniform amorphous silicon film free of defects.

従来の積層型固体撮像素子は第2図に断面図で示され、
図中、11は例えばp型のシリコン基板、12と13は
p゛型とn+型の不純物をそれぞれ拡散して形成した拡
散層、14と15は第1層と第2層の多結晶シリコン電
極、16は層間絶縁膜となるリンガラス(PSG)膜、
17はタングステン・シリサイド(W S i )膜、
18は平坦化層となるpscIg、19は例えばアルミ
ニウム(八りの画素電極(導電膜)、20はアモルファ
スシリコン(a−5i)層、21はITO(インジウム
・錫オキサイド)の透明電極、22は垂直転送用CCD
 (Charge Coupled Device)、
23は蓄積ダイオード、24は5iOz膜である。
A conventional stacked solid-state image sensor is shown in cross-section in FIG.
In the figure, 11 is, for example, a p-type silicon substrate, 12 and 13 are diffusion layers formed by diffusing p-type and n+-type impurities, respectively, and 14 and 15 are polycrystalline silicon electrodes of the first and second layers. , 16 is a phosphorus glass (PSG) film serving as an interlayer insulating film,
17 is a tungsten silicide (WS i ) film;
18 is a pscIg which becomes a flattening layer, 19 is an aluminum pixel electrode (conductive film), 20 is an amorphous silicon (a-5i) layer, 21 is an ITO (indium tin oxide) transparent electrode, and 22 is an ITO (indium tin oxide) transparent electrode. CCD for vertical transfer
(Charge Coupled Device)
23 is a storage diode, and 24 is a 5iOz film.

第2図の素子において、アモルファスシリコン層20の
下部電極である画素電極19は、平坦化層18上に導電
膜(例えばA℃膜)を被着し、しかる後にそれをエツチ
ングして個々の画素に対応して分離して形成される。な
お第2図において、27はW S i膜17と画素電極
19の接続部である。
In the device shown in FIG. 2, the pixel electrode 19, which is the lower electrode of the amorphous silicon layer 20, is formed by depositing a conductive film (for example, an A°C film) on the flattening layer 18, and then etching it to form individual pixels. are formed separately in response to the In FIG. 2, reference numeral 27 indicates a connection portion between the W Si film 17 and the pixel electrode 19.

〔発明が解決しようとする課題〕 前記した画素電極19のエツチングにおいてエツチング
で除去されずに残る縁部分が鋭角に形成されると、この
縁部分で画素電極19上に成長されるアモルファスシリ
コン層に図に符号25を付けて示すクラックが発生し、
このクラック25は画像に白く現われる画素欠陥の原因
となる。
[Problems to be Solved by the Invention] If the edge portion that remains without being removed by etching is formed at an acute angle in the etching of the pixel electrode 19 described above, the amorphous silicon layer grown on the pixel electrode 19 will be damaged at this edge portion. A crack shown with numeral 25 in the figure occurs,
This crack 25 causes a pixel defect that appears white in the image.

このようなりラック25の発生を防止するには画素電極
のエツチングされた部分の縁部が鋭角にならないように
すればよいことが確認され、画素電極のエツチングされ
た縁部分を鋭くしないための試みがなされている。その
一つはエツチングされる縁部分にテーパをつけることで
あって、そのためのエツチング方法が実験されたが、テ
ーパ状にエツチングするには工程数が増える問題があり
、またテーパを付けてもクラックの発生を完全に防止す
ることはできない現状である。
It has been confirmed that in order to prevent the occurrence of rack 25, it is sufficient to prevent the edges of the etched portion of the pixel electrode from becoming sharp. is being done. One way is to taper the edges to be etched, and experiments have been conducted on etching methods for this purpose, but etching in a tapered shape increases the number of steps, and even with a taper, cracks may occur. Currently, it is not possible to completely prevent the occurrence of.

もう一つの試みは、エツチングで除去した部分を絶縁物
で埋め込むことであるが、この方法も工程数が多く、作
業が難しいのに加えて、その方法でもクランクの発生を
防止することができない問題がある。
Another attempt is to bury the parts removed by etching with an insulating material, but this method also requires a large number of steps and is difficult to work with, and also has the problem that it cannot prevent the occurrence of cranks. There is.

そこで本発明は、画素電極となる下部電極(導電膜)を
個々の画素に対応して分離しその上にアモルファスシリ
コンを成長するにおいて、下部電極の上に成長するアモ
ルファスシリコン膜にクランクが発生することを防止す
る方法を提供することを目的とする。
Therefore, in the present invention, when a lower electrode (conductive film) that becomes a pixel electrode is separated corresponding to each pixel and amorphous silicon is grown on it, a crank occurs in the amorphous silicon film grown on the lower electrode. The purpose is to provide a method to prevent this.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は、画素電極の上にアモルファスシリコン層を
成長させる工程を含む固体撮像素子の製造において、酸
化物超伝導膜にて画素電極を形成し、該画素電極に画素
に対応してイオン注入法によって絶縁層を形成すること
を特徴とする半導体装置の製造方法によって解決される
The above problem is solved by forming a pixel electrode using an oxide superconducting film, and applying ion implantation method to the pixel electrode corresponding to the pixel in the manufacturing of a solid-state image sensor that includes a step of growing an amorphous silicon layer on the pixel electrode. The present invention is solved by a method for manufacturing a semiconductor device characterized by forming an insulating layer using the following methods.

〔作用〕[Effect]

すなわち本発明は、下部電極を個々の画素電極に分離す
るに際して従来技術における如くエツチングを用いない
ので、アモルファスシリコンが被着される下部電極の表
面に段差が全く形成されず、アモルファスシリコン層は
クラックの発生なしに形成され、クランクによる画素欠
陥が発生しなくなるのである。
That is, since the present invention does not use etching as in the prior art when separating the lower electrode into individual pixel electrodes, no step is formed on the surface of the lower electrode on which amorphous silicon is deposited, and the amorphous silicon layer is free from cracks. This eliminates the occurrence of pixel defects due to cranking.

〔実施例〕〔Example〕

以下、本発明を図示の実施例により具体的に説明する。 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

第1図は本発明実施例断面図で、第2図に示した部分と
同じ部分は同一符号を付して表示する。
FIG. 1 is a cross-sectional view of an embodiment of the present invention, and the same parts as those shown in FIG. 2 are denoted by the same reference numerals.

本発明の方法においては、第2図に示した従来例の場合
と同様に、p型のシリコン基板11にp+型抵拡散層1
2n+型型数散層13形成し、それによって垂直転送用
C0D22と蓄積ダイオード23を形成し、熱酸化によ
ってシリコン基板11の表面に5in2膜24を形成す
る。
In the method of the present invention, as in the conventional example shown in FIG.
A 2n+ type scattering layer 13 is formed, thereby forming a C0D 22 for vertical transfer and a storage diode 23, and a 5in2 film 24 is formed on the surface of the silicon substrate 11 by thermal oxidation.

次いで第1層多結晶シリコン14と第2層多結晶シリコ
ン15とから成る電極を形成し、続いて層間絶縁膜とし
てPSG膜16を堆積する。
Next, electrodes made of a first polycrystalline silicon layer 14 and a second polycrystalline silicon layer 15 are formed, and then a PSG film 16 is deposited as an interlayer insulating film.

次にWSi膜17で配線部を形成し、平坦化層としてP
SG膜18を堆積する。ここまでの工程は従来法と同一
である。
Next, a wiring part is formed using the WSi film 17, and P is used as a planarization layer.
SG film 18 is deposited. The steps up to this point are the same as the conventional method.

この表面が平坦なPSG膜18の上に画素電極をスパッ
タする。スパッタのターゲットには例えばErBa−C
u (エルビウム−バリウム−銅)合金(Er : B
a :Cu= 1 : 2.42 : 3.66 )を
用い、650°Cの温度で、Ar+(h (Ar : 
20%、oz : 4o%) 、6 Xl0−’Tor
rの雰囲気で3000人の膜厚の画素電極19aを形成
した。
A pixel electrode is sputtered onto this PSG film 18 whose surface is flat. For example, ErBa-C is used as a sputtering target.
u (erbium-barium-copper) alloy (Er: B
a:Cu=1:2.42:3.66) at a temperature of 650°C, Ar+(h(Ar:
20%, oz: 4o%), 6 Xl0-'Tor
A pixel electrode 19a having a thickness of 3,000 layers was formed in an atmosphere of R.

次に、図示しないレジストを塗布し、所定の画素パター
ンを通常の技術で形成し、かくして作られたレジストの
画素パターンをマスクにして、イオン注入法によってA
rのイオンを注入した。計イオンは加速電圧5QKeV
、ドーズ量5×10刊7cm1の条件で打ち込んだ。こ
のイオン注入によってArイオンを打ち込まれた部分2
6は、1012〜1013Ω・cmの比抵抗を示し、十
分な絶縁性をもつ絶縁層となることが確認された。
Next, a resist (not shown) is applied, a predetermined pixel pattern is formed using a conventional technique, and the pixel pattern of the resist thus created is used as a mask to perform A by ion implantation.
r ions were implanted. The meter ion has an accelerating voltage of 5QKeV
The injection was performed at a dose of 5 x 10 sheets and 7 cm1. Part 2 where Ar ions were implanted by this ion implantation
No. 6 exhibited a specific resistance of 10 12 to 10 13 Ω·cm, and it was confirmed that the insulating layer had sufficient insulation properties.

次いで、レジストを除去し、従来技術によってプラズマ
CVD装置(化学気相成長装置)で 形のアモルファス
シリコンを1μmの厚さに堆積してアモルファスシリコ
ン層20を形成し、続いてITOをスパッタ法で200
0人の厚さに堆積して透明電極21を形成した。
Next, the resist is removed, and an amorphous silicon layer 20 is formed by depositing amorphous silicon to a thickness of 1 μm using a conventional plasma CVD device (chemical vapor deposition device), and then ITO is deposited to a thickness of 200 μm by a sputtering method.
The transparent electrode 21 was formed by depositing it to a thickness of 0.03 mm.

上記の如くに形成した撮像素子において、画像にはアモ
ルファスシリコンのクラックを示す白線が認められず、
画素電極19aにはなんらのエツチングも施ざなかった
ことによりその表面に段差が形成されず、クラックの発
生が防止されたことが確認された。
In the image sensor formed as described above, no white line indicating a crack in the amorphous silicon was observed in the image.
It was confirmed that since no etching was performed on the pixel electrode 19a, no step was formed on its surface, and the occurrence of cracks was prevented.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、アモルファスシリコンが
被着される画素電極の表面に段差がなく、それによって
アモルファスシリコン層の内部にクランクが発生せず、
画質欠陥のない良好な撮像素子が形成され、それに加え
て、画素電極は超伝導体で作られているので抵抗が低く
、応答性に速い撮像素子が得られた。
As described above, according to the present invention, there is no step on the surface of the pixel electrode to which amorphous silicon is deposited, and therefore, no crank occurs inside the amorphous silicon layer.
An image sensor with good image quality and no defects was formed, and in addition, since the pixel electrode was made of a superconductor, an image sensor with low resistance and fast response was obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例断面図、 第2図は従来例断面図である。 図中、 11はシリコン基板、 12はp゛型型数散層 13はn′″型拡散拡散 層4は第1層多結晶シリコン、 15は第2層多結晶シリコン、 16はPSG膜、 17はWSi膜、 18はPSG膜、 19と19aは画素電極、 20はアモルファスシリコン層、 21は透明電極、 22は垂直転送用CCD、 23は蓄積ダイオード、 24はSiO□膜、 25はクラック、 26は絶縁層 を示す。 25−クラ・ンク 26−−−者色−く凡 FIG. 1 is a sectional view of an embodiment of the present invention. FIG. 2 is a sectional view of a conventional example. In the figure, 11 is a silicon substrate; 12 is a p-type scattered layer 13 is n''' type diffusion Layer 4 is a first layer of polycrystalline silicon, 15 is second layer polycrystalline silicon; 16 is a PSG film, 17 is a WSi film, 18 is a PSG film, 19 and 19a are pixel electrodes, 20 is an amorphous silicon layer, 21 is a transparent electrode; 22 is a CCD for vertical transfer; 23 is a storage diode, 24 is a SiO□ film, 25 is crack, 26 is an insulating layer shows. 25-Kura Nku 26--person color-kubon

Claims (1)

【特許請求の範囲】[Claims] 画素電極の上にアモルファスシリコン層を成長させる工
程を含む固体撮像素子の製造において、酸化物超伝導膜
にて画素電極(19a)を形成し、該画素電極(19a
)に画素に対応してイオン注入法によって絶縁層を形成
することを特徴とする半導体装置の製造方法。
In manufacturing a solid-state imaging device that includes a step of growing an amorphous silicon layer on a pixel electrode, a pixel electrode (19a) is formed of an oxide superconducting film, and the pixel electrode (19a) is
) A method for manufacturing a semiconductor device, comprising forming an insulating layer corresponding to a pixel by an ion implantation method.
JP1009957A 1989-01-20 1989-01-20 Manufacture of semiconductor device Pending JPH02192166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1009957A JPH02192166A (en) 1989-01-20 1989-01-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1009957A JPH02192166A (en) 1989-01-20 1989-01-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02192166A true JPH02192166A (en) 1990-07-27

Family

ID=11734428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1009957A Pending JPH02192166A (en) 1989-01-20 1989-01-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02192166A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1045450A3 (en) * 1999-04-13 2002-05-29 Agilent Technologies, Inc. (a Delaware corporation) Image sensor array device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1045450A3 (en) * 1999-04-13 2002-05-29 Agilent Technologies, Inc. (a Delaware corporation) Image sensor array device
US6586812B1 (en) 1999-04-13 2003-07-01 Agilent Technologies, Inc. Isolation of alpha silicon diode sensors through ion implantation

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