JPH02192205A - Frequency doubler - Google Patents

Abstract

PURPOSE:To make the operation stable and to improve the conversion gain by connecting a 1st gate and a drain in terms of high frequency with a proper phase delay with respect to a fundamental frequency, applying a fundamental frequency signal to a 2nd gate and connecting a band pass filter to the drain so as to extract a frequency double signal. CONSTITUTION:A phase delay circuit 12 is selected so that a phase difference between a wave made incident from a drain and appearing at a 2nd gate via a feedback capacitor and a wave made incident from a 1st gate and appearing at the 2nd gate is 180 deg.. Thus, the waves are cancelled together and the effect of a feedback capacitor is eliminated and the input is easily matched. Moreover, the wave made incident in the 1st gate is mixed with a fundamental frequency signal fed to the 2nd gate by a multiplication function of a multiplication dual gate field effect transistor(TR) (DGFET) 11 and a direct current and a signal 2fo appear at the drain (a) of the DGFET 11. Then only the wave 2fo only is selected by a band pass filter(BPF) 105 and a frequency doubler signal is extracted from an output terminal 106. Thus, the operation is made stable and the conversion gain is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Objective of the Invention 1 (Field of Industrial Application) The present invention relates to a frequency doubler using dual-gate field effect transistors.

(Prior Art) A microwave frequency multiplier is used when a high frequency signal having a desired output level, frequency stability, noise performance, etc. cannot be obtained by direct transmission or the like. In the future, multipliers will become an increasingly important component as the frequency bands used in communications and the like become higher frequency, for example millimeter waves.

A diode is a nonlinear element used in a multiplier.

There are field effect transistors (FETs) and the like. When FETs are used, conversion gain can be expected and they are suitable for monolithic microwave integrated circuits (MMICs), which are expected to develop in the future.

FIG. 3 shows a conventional example of a frequency doubler using a single gate FET (SGFET), with the bias circuit omitted for simplicity. In the same figure, 101 is 5G
FET 102 is a matching circuit for the fundamental frequency (fo), and 103 is a matching circuit for the frequency double wave (2fo).

The fundamental frequency signal is applied from the input terminal 104, and the FET
Excite the gate of Since the FET is normally biased near pinch-off, high-frequency components fo, 2fo, 3fo-nfo (1) are generated at the drain (b) point of the FET due to gate nonlinearity.

2f by band pass filter (hereinafter abbreviated as BPF) 105
.

Only the waves are taken out from the output terminal 106.

Generally, the termination condition for fo viewed from the point (b) to the BPF side is selected to be short-circuited or open in order to increase conversion efficiency. However, f reflected to the FET side at point (b)
The wave of o is applied to the gate of the FET via C by the feedback capacitance (Cr) of the FET. This fo wave interferes with the fundamental frequency signal applied to the gate, and the fO wave on the input side
It was sometimes very difficult to achieve consistency. Therefore, the termination condition viewed from point (b) on the BPF side is often selected to be slightly inductive rather than short-circuited or open-circuited.This eliminates the difficulty in matching, but the load on the multiplier becomes inductive. In the case of high temperature, unstable operation such as oscillation may occur.

(Problem to be solved by the invention) As mentioned above, conventional 5GFE! In T multipliers, it has been difficult to match the input side due to the influence of feedback capacitance, and unstable operations such as oscillation have occurred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency doubler that eliminates the difficulty of matching on the input side due to the feedback capacitance of FETs and eliminates unstable operation.

[Structure of the invention]

(Means for Solving the Problems) A frequency doubler according to the present invention has a dual-gate field effect transistor with its source grounded and an appropriate phase delay between the first gate and drain with respect to the fundamental frequency. It is characterized in that it is connected in a high frequency manner, a fundamental frequency signal is applied to the second gate, and a bandpass filter is connected to the drain, from which a frequency-doubled signal is extracted.

(Function) In the frequency doubler of the present invention, the wave of fo reflected at the drain end of the DGFET is combined with the wave that enters the second gate via the feedback capacitance, and the wave that enters the first gate via the phase delay circuit. The influence of feedback capacitance can be removed by selecting a phase difference of 180° C. between the waves that appear on the two gates.

Furthermore, since the frequency doubler of the present invention utilizes the multiplication function of the DGFET, it also has the advantage of having a higher conversion gain than a 5GFHT doubler that extracts high frequencies generated by the nonlinear operation of the FET.

(Example) An example of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a circuit diagram of a frequency doubler according to the present invention. It should be noted that parts that are the same as those described with reference to FIG. 3 in the conventional example are shown with the same reference numerals as in the conventional example, and explanations thereof will be omitted.

In FIG. 1, reference numeral 11 denotes a multiplier dual gate field effect transistor (hereinafter abbreviated as DGFET), and 12 denotes a phase delay circuit, whereby the drain and first gate of the DGFET are connected in a high frequency manner.

FIG. 2 is a diagram showing the static characteristics of the DGFET. In the frequency doubler of the present invention, the DGFET is near pinch-off (Fig. 2 A, B) or near ID5S (drain current when the source and gate are shorted with a common source and drain voltage VDS is applied) (Fig. 2). C) bias. When the fundamental frequency (fo) signal is applied to the input terminal 104, the drain-source current (Ins) of the DGFET II is switched in a rectangular waveform by the signal voltage. As a result, at the drain end (a) of DGFET II, there are fo, 3fo, 5fo, -(2n-1)fo,
---(2) signal is generated. Here, for simplicity, only fo will be considered.1 In the frequency doubler of the present invention, (
a) Select the termination condition when looking at the BPF 105 side from the point to the open state (preventing oscillation stop), so that the wave of fO reflected by the BPF is input to the drain of DGFET II and the wave of fO is input to the drain of DGFET II via the phase delay circuit 12. It can be divided into what enters the gate. Here, select a phase delay circuit so that the phase difference between the wave that enters from the drain and hits the second gate via the feedback capacitance and the wave that enters from the first gate and hits the second gate is 180°C. If they cancel each other out, the influence of the feedback capacitance can be removed, making it easier to match the input. Also, the wave incident from the first gate is DGFETI
I is mixed with the fundamental frequency signal applied to the second gate by the multiplication function of I, resulting in the drain end of DGFET II (
Direct current and 2fo are applied to a). Here, only the 2fo wave can be selected from the BPF, and the frequency doubled signal can be extracted from the output terminal 106.

In general, when a signal is input from the first gate of the DGFET 11 whose source is grounded, the DGFET has an amplification function.Therefore, the wave of fo that enters the first gate from the drain end is amplified here, and then the wave of fo is input to the second gate. It is mixed with the applied fundamental frequency signal. That is, frequency 2 of the present invention
A multiplier can be divided into a fundamental frequency signal amplifier and a frequency converter.

Therefore, compared to a 5GFET multiplier that extracts harmonic components generated by the nonlinear operation of the FET, the conversion gain is larger because it has an amplification function.

Generally, the conversion gain of 5GFET multiplier is OdB~4dB
The conversion gain of the multiplier according to the present invention is approximately 5 dB.
~6dB can be expected.

〔Effect of the invention〕

As described above, according to the present invention, it is easy to match the input, the operation is stable, and the conversion gain is excellent.
There are significant advantages that a multiplier can provide.

[Brief explanation of the drawing]

Fig. 1 is an equivalent circuit diagram of a DGFET frequency doubler according to the present invention, and Fig. 2 is an equivalent circuit diagram of a DGFET frequency doubler according to the present invention. FIG. 3 is an equivalent circuit diagram of a conventional 5GFET frequency doubler. 11 0GFET 12- Phase delay circuit 102, 10
3 Matching circuit 104
Input terminal 105----1----1----
-1--1 Band-pass filter agent Patent attorney Norifu Ogo II: DCrFLT Figure 1 3rl! J Voso VEIS Figure 2

Claims (1)

[Claims] For a dual-gate field effect transistor, the source is grounded, the first gate and drain are connected at high frequency with an appropriate phase delay with respect to the fundamental frequency, the fundamental frequency signal is applied to the second gate, and the drain A frequency doubler, characterized in that a band pass filter is connected to the frequency doubler and a frequency doubler signal is extracted from the frequency doubler.