JPH021922U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the clock signal switching circuit of the present invention, FIGS. 2 to 4 are waveform diagrams showing its operating status, and FIG. 5 is a diagram showing an embodiment of the clock signal switching circuit of the present invention. FIGS. 6 and 7 are block diagrams showing an example of a conventional clock signal switching circuit, and waveform diagrams showing its operating state. 1...Binarization circuit, 2...PLL circuit, 3...
Crystal oscillation circuit, 4...Clock signal switching circuit, 5
...Data pulse generation circuit, FF1 to FF3...
Flip-flop circuit, G1-G3, G11-G
13, G21-G23...Logic gate, IV, I
V1, IV2...Inverter.

Claims (1)

[Scope of utility model registration request] In a clock signal switching circuit that appropriately switches and outputs two clock signals having approximately the same frequency according to a switching command signal, the state of the switching command signal is read in synchronization with the first clock signal, and the state of the switching command signal is read at the rising edge of this switching command signal and Alternatively, a deletion pulse generation circuit that generates a deletion pulse corresponding to one cycle of the first clock signal at the falling edge, and a deletion pulse generation circuit that reads the state of the switching command signal in synchronization with the second clock signal and after the deletion pulse is generated. a switching pulse generation circuit that generates a switching pulse; and a switching pulse generation circuit that deletes one period of a first clock signal in response to the deletion pulse and selects the first clock signal and the second clock signal in response to the switching pulse. A clock signal switching circuit comprising a gate circuit that outputs a clock signal.