JPH02193393A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor memory device.

(Prior art) In semiconductor memory devices such as DRAM and SRAM, the level of the signal read from the memory cell onto the bit line is very small. Especially in dynamic semiconductor devices such as DRAM, the memory cell has no amplification effect. , This tendency is remarkable. Therefore, a highly sensitive sense amplifier is used in a semiconductor memory device to amplify a minute signal on a bit line during reading.

FIG. 3 shows an example of the arrangement of sense amplifiers and bit lines in a conventional semiconductor memory device. Two bit lines are connected to each sense amplifier 10. For example, in FIG. A bit line BL and a bit line BL are connected to the sense amplifier 10 shown in FIG. Each sense amplifier 10 differentially amplifies the signals on the two bit lines during reading. All sense amplifiers 10 are simultaneously driven by a sense amplifier drive signal φ outputted onto a sense amplifier drive signal line 30 from a sense amplifier drive circuit (not shown).

(Problem to be solved by the invention) By the way, between each bit line and the adjacent bit line (
For example, a capacitor C8 exists between the bit lines BL and BL. Further, a capacitance C2 exists between each bit line and the two adjacent bit lines. Among these capacitances, capacitance C8 is relatively large because the distance between corresponding bit lines is small, and is the main cause of noise due to capacitive coupling between bit lines. Semiconductor devices are becoming more highly integrated year by year, and the distance between bit lines is becoming smaller and smaller. For this reason, the level of noise caused by capacitive coupling between bit lines has become so large that it cannot be ignored compared to the level of signals read from memory cells onto bit lines. This is a major obstacle in increasing the integration and capacity of semiconductor memory devices.

The present invention was made in view of the current situation, and
The purpose is to provide a semiconductor memory device that can improve noise caused by capacitive coupling between bit lines.

(Means for Solving the Problems) A semiconductor memory device of the present invention includes a plurality of sense amplifiers each connected to two bit lines and each belonging to one of a plurality of sense amplifier groups, and a plurality of sense amplifiers each connected to two bit lines. sense amplifier driving means capable of independently driving each of the amplifier groups; and means for maintaining constant the voltage of a bit line connected to a sense amplifier belonging to a sense amplifier group not driven by the sense amplifier driving means. A bit line connected to a sense amplifier belonging to another sense amplifier group is arranged between two bit lines connected to a sense amplifier belonging to each sense amplifier group, thereby achieving the above purpose. is achieved.

(Example) The invention will now be described with reference to examples.

FIG. 1 schematically shows the arrangement of sense amplifiers and bit lines in an embodiment of the present invention. In this embodiment, one of a series of sense amplifiers 1, 2, 3, . . . odd-numbered sense amplifiers 1.3 connected to signal line 3;
... n-1 belongs to the first sense amplifier group, and even-numbered sense amplifiers 2.4, . . . n connected to the sense amplifier drive signal line 4 belong to the second sense amplifier group.

Sense amplifiers 1.3, belonging to the first sense amplifier group,
... are driven by the sense amplifier drive signal φ on the sense amplifier drive signal line 3. On the other hand, the sense amplifiers 2, 4, . . . belonging to the second sense amplifier group receive the sense amplifier drive signal φ2 on the sense amplifier drive signal line 4.
driven by.

The sense amplifier 1 includes two bit lines BL and BL.
are connected, and the sense amplifier 1 differentially amplifies signals read onto these bit lines from memory cells or dummy cells (not shown). Bit line BL is connected to sense amplifier 2.
2 and BL2 are connected. A bit line BL connected to the sense amplifier 1 and a bit line BL2 connected to the sense amplifier 2 are arranged between the bit lines BL and BL. On the other hand, bit line B connected to sense amplifier 2
In this embodiment, a bit line BL connected to the sense amplifier 1 is arranged between L2 and BL2.
Of the bit lines connected to the sense amplifier 1 and the bit lines connected to the sense amplifier 2, the bit line BL and the bit line BL2 are crossed in the vicinity of the sense amplifier 1 and the sense amplifier 2 to achieve this effect. A suitable bit line arrangement has been realized. Regarding the bit lines connected to the sense amplifiers 3 belonging to the first sense amplifier group and the sense amplifiers 4 belonging to the second sense amplifier group, similarly, the bit lines BL connected to the sense amplifiers 3 and A bit line BL connected to the sense amplifier 4 is arranged between the bit lines BL3 and BL3. In this way, in this embodiment, between the two bit lines connected to the sense amplifiers of each sense amplifier group, one of the bit lines connected to the sense amplifiers belonging to the other sense amplifier groups is connected. A bit line is provided.

A precharge voltage is applied to the signal line 5.

The bit lines connected to the sense amplifiers 1.3, . . . of the first sense amplifier group are connected to the signal line 5 via a transistor 61. On the other hand, the bit lines connected to the sense amplifiers 2.4, . . . of the second sense amplifier group are connected to the signal line 5 via the transistor 71. The bit lines connected to the sense amplifiers 1.3, . . . are charged to a precharge voltage by a precharge signal applied to the signal line 6. sense amplifier 2
．． The bit lines connected to the bit lines 4, . . . are charged to a precharge voltage by a precharge signal applied to the signal line 7.

During reading, a sense amplifier drive circuit (not shown) sometimes activates only one of the sense amplifier drive signals φ and φ2.

For example, when only sense amplifier drive signal φ1 is activated, sense amplifier 1 of the first sense amplifier group
．． 3, . . . are driven, and the bit lines connected to those sense amplifiers are sensed. sense amplifier 1.3,
... are operating, the sense amplifiers 2.4, ... of the second sense amplifier group are inactive, and the bit lines connected to the sense amplifiers 2.4, ... are in the preamp state. Remains charged.

When the sense amplifier drive signal φ2 is activated and the sense amplifiers 2.4, . . . are operating, the bit lines connected to the sense amplifiers 1.3, . be done.

When the sense amplifiers 1.3, . . . are driven, for example, if we pay attention to the bit line BL, the bit line BL2
Since the bit line BL2 acts as a shield line, noise through the capacitor C1 can be ignored, and noise that directly affects the bit line T is limited to through the capacitor C2. The same is true for each bit line being sensed by the sense amplifier. Since the noise through the capacitor C2 is much smaller than the noise through the capacitor C4, the noise generated between the bit lines in this embodiment is significantly improved compared to the conventional one.

FIG. 2 schematically shows the arrangement of sense amplifiers and bit lines in a second embodiment of the present invention. In FIG. In the embodiment, two bit lines BL and BL connected to the sense amplifier 1 belonging to the first sense amplifier group
, a sense amplifier 22 belonging to the second sense amplifier group and a sense amplifier 2 belonging to the third sense amplifier group
Bit lines BL2 and BL3 are provided, which are connected to the bit lines BL2 and BL3, respectively. The two bit lines connected to the sense amplifiers 22 and 23 are also connected to sense amplifiers belonging to a different sense amplifier group from the sense amplifier group to which the sense amplifiers to which those bit lines are connected belong. Two bit lines are provided.

At the time of reading, one of the sense amplifier drive signals φ7, φ2, and φ3 is activated by the sense amplifier drive circuit outside the area. For example, the sense amplifier drive signal φ
, is activated, the 3i+1 (i is an integer greater than or equal to 0) sense amplifier belonging to the first sense amplifier group is driven, and the bit lines connected to these sense amplifiers are sensed. While these sense amplifiers are operating, bit lines connected to sense amplifiers of other sense amplifier groups are held in a precharged state.

Therefore, in this embodiment, not only the noise due to the capacitance C1 between adjacent bit lines, but also the noise due to the capacitance C2 between two adjacent bit lines can be ignored, and the noise generated between the bit lines can be minimized. can be made into something.

<Effects of the Invention> According to the present invention, a semiconductor memory device is provided that can significantly improve noise caused by capacitive coupling between bit lines. Therefore, in the semiconductor memory device of the present invention, high integration can be achieved while maintaining reliability during reading.

,':I f:Day FIG. 1 is a diagram schematically showing the arrangement of sense amplifiers and bit lines in the first embodiment of the present invention, and FIG. FIG. 3 is a diagram schematically showing the arrangement of sense amplifiers and bit lines in a conventional example.

1.3, n-1, 21... sense amplifier belonging to the first sense amplifier group, 2.4, n, 22... sense amplifier belonging to the second sense amplifier group, 23... third sense amplifier Sense amplifier belonging to the sense amplifier group, 5... Signal line for applying precharge voltage, 6.7... Signal line for precharge signal, 61.71... Transistor for precharge, BL, BL, , BL2, BL2, BL3, BL3
,BL4,BL,,BLn,,BL,-1,BL,,B
L...Bit line.

that's all

Claims (1)

[Claims] 1. A plurality of sense amplifiers each connected to two bit lines and each belonging to one of a plurality of sense amplifier groups; and independently driving each of the plurality of sense amplifier groups. and a means for maintaining constant the voltage of a bit line connected to a sense amplifier belonging to a sense amplifier group that is not driven by the sense amplifier driving means, 2 connected to sense amplifier
A semiconductor memory device in which bit lines connected to sense amplifiers belonging to other sense amplifier groups are arranged between two bit lines.