JPH021942A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device constituted so as to be able to apply effectively a given space without being subject to restriction and restrain on the arrangement of each aperture by a method wherein each aperture is formed on each field insulating film, other end part of a multilayer film is made to face in opposition to a gate electrode on the gate electrode covered with an insulating film and the aperture of the gate electrode is formed in a self-alignment manner. CONSTITUTION:In each conducting film 17, each insulating film 18 is selectively removed on each field insulating film 13 to expose part of each film 17, and apertures 22 to source and drain regions 16 are formed. After that, such a wiring material as Al is adhered on the surface including these apertures 21, 22 and 22 and moreover, this is patterned as is expected to form wiring layers 23 and 24 in the respective apertures. As a result, the layer 23 to a gate electrode 14 is connected to the electrode 14 and formed directly over the electrode 14 in the aperture 21 on one side and each wiring layer 24 to each region 16 is connected to each region 16 and formed on each film 13 in each aperture 22 on the other side. Accordingly, the gate electrode and the source and drain regions can be integrated in a high density.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, improvements in the arrangement and connection structure of each wiring layer in an MO5 field effect transistor and the method for manufacturing the same. This is related to.

(Prior Art) As a conventional semiconductor device of this type, in this S, the main manufacturing steps of an MO5 field effect transistor are shown in order of process in FIGS. 4(a) to 4(c), and FIG. FIG. 4(C) shows the planar pattern after the process is completed.

In these FIGS. 4(a) to 4(c), the MO5 field effect transistor according to the conventional example first has a predetermined active region range 2 on a silicon semiconductor substrate l of a first conductivity type, in this case a p-type. A thick field insulation @ 3 is formed for isolation between elements by leaving a part of the active region 2 on the main surface of the semiconductor substrate 1 within this active region range 2. A gate electrode whose portion and side portions are covered with an insulating film 5a such as an oxide film, and whose lower surface portion is interposed with a gate insulating film 5b.

For example, the gate electrode 4 made of a polycrystalline silicon layer doped with impurities is selectively provided, and the field insulation E13. Then, using the insulating film 5a covering the gate electrode 4 as a mask, a second conductivity type, for example, an n-type material such as phosphorus or arsenic, is implanted into the main surface of the semiconductor substrate l by ion implantation. Impurities are implanted at a high concentration to selectively form n-type source and drain regions 6 (FIG. 3(b)).

Subsequently, an interlayer insulating film 7 such as an oxide film is formed on these entire surfaces.
is deposited, and portions of this interlayer insulating film 7 corresponding to the source and drain regions 6 are selectively removed to form respective openings 8a that will become contact holes. In order to avoid a short circuit between the electrode 4 and the wiring layer to be formed subsequently, the gate electrode 4 and each opening 8a are positioned so as to be separated by a distance @d S, and then, A wiring layer 9 for each of the source and drain regions 6 is selected by depositing a wiring material such as A4 through each of these openings 8a and patterning it as desired. ((C) of the same figure).

In addition, a wiring layer (not shown) for the above gate type J44
As shown in FIG. 5, which is a planar pattern after the step shown in FIG. 4(C), the gate electrode 4 is extended over the one field insulation@3,
Each opening 8a for each of the source and drain regions 6
At the time of formation, an opening 8b for the gate electrode 4 is similarly formed selectively at the position of the field insulating film 3, and connection is made through this opening 8b.

That is, with the device configuration manufactured through the steps described below, a desired MO5 field effect transistor in which each wiring layer is connected to each gate electrode, source, and drain region is obtained.

[Problem to be solved by the invention]

However, the conventional MO5 type field effect transistor configured as described above has a high density! ＆For each gate electrode, source, and drain region formed as close as possible to each other under stacking, each gap [1 part is formed] to connect the wiring layer to each region. Although,
There are disadvantages in that extra space must be secured and there are also restrictions on the location of each opening, and these points make it difficult to achieve even higher density integration of device configurations. It was a hindrance to

This invention was made to solve these conventional problems, and its purpose is to improve the connection of each opening to each wiring connection to the gate electrode, source, and drain regions. There are no restrictions or restrictions on placement, and the space provided can be used effectively. A second object of this type of semiconductor device and method of manufacturing the same is to provide an MO5 field effect transistor and a method of manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device and a method for manufacturing the same according to the present invention provide a semiconductor device and a method for manufacturing the same, which do not directly form openings serving as contact holes with wiring layers in each of the source and drain regions.

From each region of the drain, one end of the multilayer film consisting of a conductive layer and an insulating film is extended onto the field insulating film to form an opening on the field insulating film. The end portion faces a gate electrode covered with an insulating film, and the opening of the gate electrode is formed in a self-aligned manner.

That is, the present invention provides a gate electrode that is provided on the main surface of a first conductivity type semiconductor substrate surrounded by a thick field insulating film, with a gate insulating film interposed therebetween, and whose surface portion is covered with the insulating film; source and drain regions of the second conductivity type formed by diffusion across the gate electrode, and in contact with these source and drain regions, one end extending over the field insulating film and the other end. and a multilayer film consisting of an insulating film covering the four electrically conductive films facing each other on the insulating film of the gate electrode, and a multilayer film consisting of an insulating film covering the four electrically conductive films facing each other on the insulating film of the gate electrode. The insulating film is formed in a self-aligned manner, and the gate electrode between the opposing surfaces is exposed to form an opening, and the insulating film of the multilayer film in the field insulating film is partially removed to form a conductive film. A semiconductor device is characterized in that openings are exposed and wiring layers are connected through these openings, and the main surface of a semiconductor substrate of a first conductivity type is surrounded by a thick field insulating film. A step of providing a gate electrode having an upper surface and side surfaces covered with an insulating film and a gate insulating film interposed on the lower surface, and using the gate electrode covered with the insulating film as a mask, the semiconductor according to r11. A step of ion-implanting impurities of a second conductivity type onto the main surface of the substrate to form source and drain regions by diffusion, and a step of forming one end in contact with the outer regions of the source and drain.
A conductive film extending over the field insulating film, the other end of which faces the insulating film of the gate electrode.

and a step of selectively forming a multilayer film consisting of an insulating film covering the gate electrode, and a step of depositing an insulating film on the entire surface of these, and then forming a multilayer film of an insulating film and a conductive film facing above the gate electrode. Step of exposing the opposing surfaces, forming an insulating film on each exposed opposing surface in a self-aligned manner, and selectively exposing the surface of the gate electrode surrounded by the insulating film to form an opening. Then, the insulating film of each multilayer film extended on the field insulating film in contact with each region of the source and drain described in 111 is selectively removed on this field insulating film to selectively remove the surface of each conductive film. forming an opening by exposing the wiring layer to the gate electrode, and depositing a wiring material on the surface including the spaces [ ], and patterning the wiring material to form a wiring layer for the gate electrode, and for each of the source and drain. 1. A method of manufacturing a conductor device, comprising a step of connecting each wiring layer to a region.

[For production]

Therefore, in the present invention, an opening 1 is provided for each of the source and drain regions to serve as a contact hole with the wiring layer.
The same source without forming the part directly.

From each region of the drain, one end of the multilayer film consisting of a conductive film and an insulating film is extended onto the field insulating film to form an opening on the field insulating film, and the other end of the multilayer film is extended onto the field insulating film. The open part of the gate electrode was formed in a self-aligned manner, so that the gate electrode and the source,
It does not require any extra space to form the respective wiring connections for each region of the drain, and it can be easily formed without being subject to any restrictions on the placement position. One part of the opening can be formed in a self-aligned manner.

(Example) Hereinafter, an example of a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to FIGS. 1 to 3.

FIG. 1(a) to e) shows an MO to which this embodiment is applied.
Each is a cross-sectional view schematically showing the main manufacturing steps of a 5-type field effect transistor in the order of steps, and FIG. (e)
FIG. 3 is an explanatory plan view showing each planar pattern after the process is completed.

Also in FIGS. 1(a) to 1(e), the MO5 field effect transistor according to this embodiment first has a predetermined active region range 12 on a silicon semiconductor substrate 11 of a first conductivity type, that is, a p-type. , and form a thick field insulating film 13 for isolation between elements (as shown in the same figure).
a)), then the silicon semiconductor substrate within this active region area 12! The gate electrode 0 is located on the main surface of (2), whose upper surface and side surfaces are covered with an insulating film 15a such as an oxide film, and whose lower surface is interposed with a gate insulating film 15b. A gate electrode I4 made of a crystalline silicon layer or the like is provided, and these field insulating films 13. Using the insulator 11 covering the gate electrode 15a as a mask, a second conductivity type, that is, an n-type material such as phosphorus or arsenic, is added to the surface of the silicon semiconductor substrate II by, for example, ion implantation. An n-type source is created by implanting a high concentration of impurities.

Each region 16 of the drain is formed separately (see FIG.
b)).

Subsequently, a conductive film 17 made of, for example, a polycrystalline silicon layer doped with impurities, and an insulating film 18 such as an oxide film are sequentially formed on these entire surfaces to form a multilayer model. At least with respect to the former conductive film 17, one end thereof is covered with the field insulating film 1 while completely covering the exposed portions of the source and drain regions 16.
3, and the other end is connected to the gate electrode 1.
The insulating film 15a covering the conductor 4 is placed so as to face the insulating film 15a covering the
The field insulating film 13 and the insulating film 15 are removed by selectively patterning and removing the multilayer film consisting of the
A is exposed ((C) in the same figure).

After that, these field insulating films 13 . After depositing an interlayer insulating film 19 such as an oxide film again on the entire surface of each exposed portion of the insulating film 15a, a part of the surface of the insulating film 15a at the gate electrode 14,
Insulating film 18 facing above. The opposite surfaces of the ends of the multilayer film made of the conductive film 17 are exposed (corresponding to the reference numeral 20 in FIG. 2), and the insulating films 19a are respectively formed on the opposite surfaces of the exposed ends of the multilayer film. The insulating film 15 is formed in a self-aligned manner and is surrounded by the insulating film 19a.
a to selectively expose a part of the surface of the gate electrode 14, and in this way, the opening 21 of the gate electrode 14 is removed.
((d) in the same figure).

Also, each of the source and drain regions! 6 and extending on the field insulating film 13 respectively.
17, the respective conductive films 18 are selectively removed on each field insulating film 13 to expose a part of each conductive film 17.
1i17. Furthermore, openings 22 for each of the source and drain regions 16 are formed, and then a wiring material such as A2 is deposited on the surface including each of these openings 21 and 22.22, and this is placed in place. This is the result of patterning as planned to form wiring layers 2:1 and 24, respectively.

Depending on the opening 21 on one side, the wiring layer 23 for the gate electrode 14 is connected directly above it, and each opening 2 on the other side
2, each wiring layer 24 for each source and drain region 6 is connected to each field insulating film 13 . They are connected to each other at I: (FIG. 3(e)), and the planar pattern after this process is as shown in FIG.

That is, in this example, the device configuration manufactured through the above steps allows for high-density integration of the gate electrode, source, and drain regions, as well as the arrangement and connection of each wiring layer to these regions. In this way, the first MO5 type field effect transistor was obtained.

Therefore, the N-channel MO configured according to this embodiment
In the case of a type 5 field effect transistor, the opening 21 for the gate electrode 14 does not need to extend the gate electrode 4 to the field insulating film 3F as in the conventional configuration, and can be formed at any position of the gate electrode 1jll. Furthermore, the openings 22 for the source and drain regions 16 are not formed directly on the source and drain regions 16, but are formed on the conductive layer 17 drawn out from the respective regions 16. Therefore, a sufficient degree of freedom in the arrangement position of the five-way opening 22 is ensured, which makes it possible to narrow the source and drain regions 16, thereby reducing the device performance due to an increase in the source and drain resistance. etc. can be prevented.

〔Effect of the invention〕

As detailed above, according to the present invention, the arrangement of each wiring layer in a MOS field effect transistor.

In the connection structure, a multilayer film of a conductive film and an insulating film is formed from each source and drain region without directly forming an opening that becomes a contact hole with the wiring layer. One pane extends over the field insulating film to form an opening on the field insulating film, and the other end of the multilayer fIQ faces the gate electrode 1- covered with the insulating film. Since the opening 1] of the gate electrode is formed in a self-aligned manner, in order to set the arrangement of each opening that makes wiring connections to the gate electrode and each source and drain region, This eliminates the need for additional space and allows flexibility in the placement of each of these openings, allowing the semiconductor substrate to be
The device configuration space at L can be effectively and well utilized.In addition, the gate electrode opening can be formed in a self-aligned manner, reducing the required space. As such, it has excellent features such as being able to achieve even higher density integration of the device configuration.

[Brief explanation of the drawing]

1(a) to 1(e) are cross-sectional views schematically showing the main manufacturing steps of an MO5 field effect transistor according to an embodiment of the present invention in order of process, and FIG.
FIG. 3 after the completion of the process in FIG. 1(d) is an explanatory diagram showing the planar pattern of FIG.
In addition, FIG. 4(a) to C) shows the same FM according to the conventional example.
FIG. 5 is a sectional view schematically showing the main manufacturing steps of an O5 field effect transistor in order of process, and FIG.
C) It is an explanatory view showing a plane pattern after the process is completed. 11...Silicon semiconductor substrate, 12...Active region range, 13...Field insulating film, 14...
Gate electrode, 15a... Insulating film covering the gate electrode, +5b... Gate insulating film, 16... Source and drain regions, 17... Conductive film, 18...
An insulating film on a conductive film! 9... Interlayer insulating film, 19a.
... Insulating film on the opposing surface, 21 ... Opening of gate electrode, 22 ... Opening of each source and drain region, 2
3... Wiring layer with the gate electrode, 24... Wiring layer with the source and drain regions. Figure 1 Agent Masu Oiwa Yutoku V pieces'x-
cQ Keida ■ Disaster diagram number? Figure Figure Figure 5

Claims (2)

[Claims] (1) provided on the main surface surrounded by a thick field insulating film of a semiconductor substrate of the first conductivity type, with a gate insulating film interposed therebetween;
A gate electrode whose surface portion is covered with an insulating film, a second conductivity type source and drain region formed by diffusion across the gate electrode, and one end portion in contact with each of the source and drain regions. extends on the field insulating film,
A conductive film whose other end faces the insulating film of the gate electrode, and a multilayer film consisting of an insulating film covering the conductive film, the multilayer films facing each other on the insulating film of the gate electrode. An insulating film is formed on the field insulating film in a self-aligned manner, and the gate electrode between the opposing faces is exposed to form an opening, and a portion of the insulating film of each multilayer film on the field insulating film is removed to form a conductive film. A semiconductor device characterized in that a film is exposed to form openings, and wiring layers are connected and formed through each of these openings. (2) A gate electrode is provided on the main surface of the first conductivity type semiconductor substrate surrounded by a thick field insulating film, the top surface and side surfaces of which are covered with an insulating film, and the bottom surface of which is covered with a gate insulating film. and a step of ion-implanting impurities of a second conductivity type onto the main surface of the semiconductor substrate using the gate electrode covered with the insulating film as a mask to form source and drain regions by diffusion. , a conductive film in contact with each of the source and drain regions, one end of which extends over the field insulating film, and the other end of which faces the gate electrode insulating film; A step of selectively forming a multilayer film consisting of an insulating film to cover the gate electrode, and after depositing an insulating film on the entire surface of the insulating film, an opposing surface of the multilayer film consisting of an insulating film and a conductive film facing above the gate electrode is formed. , exposing and forming an insulating film in a self-aligned manner on each of the exposed opposing surfaces, and selectively exposing the surface of the gate electrode surrounded by the insulating film to form an opening; The insulating film of each multilayer film extending on the field insulating film in contact with each of the source and drain regions is selectively removed on the field insulating film to selectively expose the surface of each conductive film. forming a wiring layer for the gate electrode, a wiring layer for the gate electrode, a wiring layer for the gate electrode, a wiring layer for the gate electrode, and a step for depositing a wiring material on the surface including each opening, and patterning the wiring material.
1. A method of manufacturing a semiconductor device, comprising the step of connecting each wiring layer to each region of a drain.