JPH021942U

JPH021942U -

Info

Publication number: JPH021942U
Application number: JP8030788U
Authority: JP
Priority date: 1988-06-16
Filing date: 1988-06-16
Publication date: 1990-01-09

Description

[Brief explanation of drawings]

第１図ａ，ｂは本考案の実施例を示し、ａは送
信側、ｂは受信側のブロツク図である。１……送信データ、２……送信書き込みクロツ
ク、３……送信書き込みカウンタ、４……送信記
憶フリツプフロツプ、５……送信書き込みタイミ
ングパルス、６……送信記憶データ、７……送信
読み出しゲート回路、８……送信読み出しカウン
タ、９……送信読み出しタイミングパルス、１０
……送信位相比較器、１１……送信読み出しデー
タ、１２……送信読み出しクロツク、１３……送
信位相比較信号、１４……受信データ、１５……
受信書き込みクロツク、１６……受信書き込みカ
ウンタ、１７……受信記憶フリツプフロツプ、１
８……受信書き込みタイミングパルス、１９……
受信記憶データ、２０……受信読み出しゲート回
路、２１……受信読み出しカウンタ、２２……受
信読み出しタイミングパルス、２３……受信位相
比較器、２４……受信読み出しデータ、２５……
受信読み出しクロツク、２６……受信位相比較信
号。 FIGS. 1a and 1b show an embodiment of the present invention, in which a is a block diagram of the transmitting side and b is a block diagram of the receiving side. 1... Transmission data, 2... Transmission write clock, 3... Transmission write counter, 4... Transmission memory flip-flop, 5... Transmission write timing pulse, 6... Transmission memory data, 7... Transmission read gate circuit, 8... Transmission read counter, 9... Transmission read timing pulse, 10
... Transmission phase comparator, 11 ... Transmission read data, 12 ... Transmission read clock, 13 ... Transmission phase comparison signal, 14 ... Reception data, 15 ...
Receive write clock, 16...Receive write counter, 17...Receive memory flip-flop, 1
8... Reception write timing pulse, 19...
Reception storage data, 20...Reception readout gate circuit, 21...Reception readout counter, 22...Reception readout timing pulse, 23...Reception phase comparator, 24...Reception readout data, 25...
Reception readout clock, 26...reception phase comparison signal.

Claims

[Claims for Utility Model Registration] A digital high-speed demultiplexing device, comprising: a transmission channel section having n flip-flops for storing transmission data; and a write counter for writing the transmission data into the n flip-flops; a read counter that generates timing pulses for reading n pieces of memory data stored in the n flip-flops; and a gate that converts the n pieces of memory data into one data string using the timing pulses from the read counter. a multiplexer having a circuit and a phase comparator for comparing the phases of a write clock and a read clock; n flip-flops for storing multiplexed received data; and writing the received data to the n flip-flops. a separator having write counters of n and n flip-flops stored in the separator.
Compare the phases of the read counter that generates timing pulses for reading n stored data, the gate circuit that converts those n stored data into one data string using the timing pulses from the read counter, and the write clock and read clock. A digital high-speed demultiplexing device having a phase comparator for demultiplexing and a receiving channel section having a phase comparator for demultiplexing.