JPH02194592A - Manufacture of multi-layer wiring board - Google Patents

Manufacture of multi-layer wiring board

Info

Publication number
JPH02194592A
JPH02194592A JP1377889A JP1377889A JPH02194592A JP H02194592 A JPH02194592 A JP H02194592A JP 1377889 A JP1377889 A JP 1377889A JP 1377889 A JP1377889 A JP 1377889A JP H02194592 A JPH02194592 A JP H02194592A
Authority
JP
Japan
Prior art keywords
insulating
insulating ink
ink
insulation
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1377889A
Other languages
Japanese (ja)
Inventor
Tokisada Takeda
時定 竹田
Satoshi Isoda
聡 磯田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi Condenser Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Condenser Co Ltd filed Critical Hitachi Condenser Co Ltd
Priority to JP1377889A priority Critical patent/JPH02194592A/en
Publication of JPH02194592A publication Critical patent/JPH02194592A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To prevent warpage of an insulation substrate, thus reducing scattering of the thickness of an insulation layer and obtain a multi-layer wiring board without producing any crack in the insulation layer by forming the insulation layer, applying insulating ink onto both surfaces of the insulation substrate alternately. CONSTITUTION:A circuit 2 is formed by etching, for example, a copper foil of a copper-clad insulation substrate 1 and an insulating ink is applied to the entire surface of the insulation substrate 1. Furthermore, an insulating ink 4 is applied to the other surface of the insulation substrate 1 for curing. An insulating ink 5 is applied to the surface of the insulating ink 3 again for curing and forming an insulation layer 6. In similar manner, an insulation ink 7 is applied to the surface of the insulating ink 4 for curing and forming an insulation layer 8.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は多属配線板の製造方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing a multi-metal wiring board.

(従来の技術) 従来、多属配線板を製造する方法は、例えば銅箔を張り
付けた絶縁基板を用い、この銅箔表面にエツチングを塗
布し、次いでエツチングを行って回路を形成する。そし
てエツチングにより回路を形成した後、片面にスクリー
ン印刷法によって絶縁性インクを塗布し硬化して絶縁層
を形成する。
(Prior Art) Conventionally, a method for manufacturing a multi-metal wiring board involves using, for example, an insulating substrate with copper foil pasted thereon, applying etching to the surface of the copper foil, and then performing etching to form a circuit. After forming a circuit by etching, insulating ink is applied to one side by screen printing and hardened to form an insulating layer.

片面に絶縁製を形成後、他面に同Φの絶縁性インクを塗
布・硬化して絶縁層を形成する。
After forming an insulating layer on one side, an insulating ink having the same diameter is applied and cured on the other side to form an insulating layer.

(発明が解決しようとする課題) しかし、従来は、絶縁性インクを一回だCノ塗イnして
絶縁層を形成しているために、塗布厚が厚くなり、塗イ
i後の絶縁性インクを硬化すると絶縁基板が大きく反る
欠点が生じる。絶縁基板の反りが大きくなると、他面に
絶縁性インクを塗15 シた際にその厚さが均一になら
ない欠点がある。
(Problem to be solved by the invention) However, in the past, since the insulating layer was formed by applying insulating ink only once, the thickness of the application became thick, and the insulation after application When the adhesive ink is cured, there is a drawback that the insulating substrate is greatly warped. If the warpage of the insulating substrate becomes large, there is a drawback that the thickness of the insulating ink will not be uniform when applied to the other surface.

この欠点を防止するために、絶縁性インクを塗布した後
に、絶縁基板の反りを機械的に直す法もあるが、絶縁層
にクラックを生じ易い欠点がある。
In order to prevent this drawback, there is a method of mechanically correcting the warpage of the insulating substrate after applying the insulating ink, but this method has the drawback of easily causing cracks in the insulating layer.

本発明の目的は、上記の目的を達成するために、絶縁基
板の大きな反りを防止し、絶縁性インクの塗布厚を均一
にでき絶縁層にクラックを生じるのを防止しうる多属配
線板の製造方法を提供するものである。
In order to achieve the above objects, an object of the present invention is to provide a multi-metal wiring board that can prevent large warping of an insulating substrate, make the coating thickness of insulating ink uniform, and prevent cracks from occurring in the insulating layer. A manufacturing method is provided.

(課題を解決するための手段) 本発明は、上記の目的を達成するために、絶縁基板の両
面に複数回に分けて交互に絶縁性インクを?8布して所
定厚さの絶縁図を形成することを特徴とする多属配線板
の製造方法を提供するものである。
(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention applies insulating ink alternately to both surfaces of an insulating substrate in multiple steps. The present invention provides a method for manufacturing a multi-metal wiring board, which is characterized in that an insulation diagram of a predetermined thickness is formed using eight cloths.

(作用) 本発明によれば、絶縁基板の一面に絶縁性インクを塗布
した後、他面に絶縁性インクを塗布し、再び前の面に絶
縁性インクを塗布する1稈を必要回数だけ繰り返し、所
定の厚さの絶R層を形成できる。従って、−回の絶縁性
インクの塗布摩を薄くでき、また、両面の塗布摩の差を
小さくできるために、絶縁基板の反りを軽減でさる。
(Function) According to the present invention, after applying insulating ink to one side of the insulating substrate, insulating ink is applied to the other side, and insulating ink is applied again to the previous side, which is repeated as many times as necessary. , it is possible to form an absolute R layer with a predetermined thickness. Therefore, it is possible to reduce the amount of application friction of the insulating ink between the two times, and also to reduce the difference in the amount of application friction between both sides, thereby reducing warping of the insulating substrate.

(実施例) 以下、本弁明を図示の実施例に基づいて説明する。(Example) The present invention will be explained below based on illustrated embodiments.

先ず、第1図に示す通り、銅張りI8縁基板1の銅箔を
エツチングして回路2を形成する。
First, as shown in FIG. 1, a circuit 2 is formed by etching the copper foil of a copper-clad I8 edge board 1.

次に、第2図に示V通り、絶縁基板1の一面に絶縁性イ
ンク3をスクリーン印刷やロールエンコーダによりm 
イIT L硬化する。
Next, as shown in FIG.
IT L hardens.

さらに、第3図に示す通り、絶縁基板1の他面に絶縁性
インク4を塗布し硬化する。
Furthermore, as shown in FIG. 3, an insulating ink 4 is applied to the other surface of the insulating substrate 1 and cured.

絶縁性インク4を塗布後、第4図に示す通り再び絶縁性
インク3の表面に絶縁性インク5を塗布し硬化して絶縁
層6を形成する。そして同様に、第5図に示す通り絶縁
性インク4の表面に絶縁性インク7を塗布し硬化して絶
縁層8を形成する。
After applying the insulating ink 4, as shown in FIG. 4, an insulating ink 5 is again applied to the surface of the insulating ink 3 and cured to form an insulating layer 6. Similarly, as shown in FIG. 5, an insulating ink 7 is applied to the surface of the insulating ink 4 and cured to form an insulating layer 8.

なお、絶縁層6及び8は、絶縁性インクを各2回交互に
繰り返して塗布し形成しているが、少なくともどららか
一方を2回以上塗布して形成すればよい。
Although the insulating layers 6 and 8 are formed by alternately applying insulating ink twice each, they may be formed by applying at least one of them two or more times.

例えば、どちらか一方の絶縁層が絶縁性インクを一回塗
布して形成することができるならば、他方の絶縁層は絶
縁性インクを2回繰り返してi′会布し硬化して形成し
てもよい。
For example, if one of the insulating layers can be formed by applying the insulating ink once, the other insulating layer can be formed by applying the insulating ink twice and curing it. Good too.

また、両方の絶縁層とも、絶縁性インクを3回以上繰り
返して塗布し硬化して形成してもよい。
Further, both insulating layers may be formed by repeatedly applying insulating ink three or more times and curing it.

次に、本発明実施例と従来例とについて、厚さ200μ
mの絶縁層を形成した後の厚さの最大値と最小値とを測
定した。本発明実施例と従来例の製造方法は次の通りで
ある。
Next, regarding the embodiment of the present invention and the conventional example, the thickness is 200 μm.
After forming an insulating layer of m, the maximum and minimum thicknesses were measured. The manufacturing methods of the embodiment of the present invention and the conventional example are as follows.

本発明実施例、 絶縁性インクを表1の通り、各々2回交互にスクリーン
印刷により塗イ■し、各塗布後に温度120℃の雰囲気
中で60分間乾燥し、ざらに最(νに温度180℃の雰
囲気中で90分間乾燥し硬化して絶縁Nを形成する。
Example of the present invention: As shown in Table 1, the insulating ink was applied twice by screen printing alternately, and after each application, it was dried for 60 minutes in an atmosphere at a temperature of 120°C. The insulation N is formed by drying and curing in an atmosphere at .degree. C. for 90 minutes.

表1 に、同じ条件で絶縁性インクを塗布・乾燥し硬化して絶
縁図を形成する。
In Table 1, insulating ink is applied, dried, and cured under the same conditions to form an insulation diagram.

測定結果は表2の通りとなった。The measurement results are shown in Table 2.

表2 従来例、 絶縁基板の一面に、20メツシユの版を用いてスクリー
ン印刷により絶縁性インクを厚さ20μm1.:;’z
布し、温度120℃の雰囲気中で60分間乾燥して硬化
す゛る。次に、他面表2から明かな通り、絶縁層の厚さ
の範囲は、厚さ200μ肌に対して、本発明実施例が−
9〜+7.5%、従来例が−14,5−+13%となり
、前者の方が明かに厚さのバラツキが少ない。
Table 2 Conventional example: Insulating ink was applied to one side of an insulating substrate to a thickness of 20 μm by screen printing using a 20-mesh plate. :;'z
It was dried for 60 minutes in an atmosphere at a temperature of 120° C. to harden it. Next, as is clear from Table 2, the range of the thickness of the insulating layer is -
9 to +7.5%, and -14.5-+13% for the conventional example, with the former having clearly less variation in thickness.

(発明の効果) 以トの通り、本発明の製造方法によれば、絶縁基板の両
面に交互に絶縁性インクを塗布して絶縁層を形成してい
るために、絶縁基板の反りを防止して絶縁層の厚さのバ
ラツキを低くでき、絶縁層にクラックを生じることのな
い多属配線板が得られる。
(Effects of the Invention) As described above, according to the manufacturing method of the present invention, since the insulating ink is applied alternately to both sides of the insulating substrate to form an insulating layer, warping of the insulating substrate can be prevented. As a result, variations in the thickness of the insulating layer can be reduced, and a multi-metal wiring board without cracks in the insulating layer can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第5図は本発明の製造工程を示ザ多属配線板の
断面図である。 1・・・絶縁基板、 2・・・回路、 3.4..5.7・・・絶縁性インク、6.8・・・絶
縁層。 特許出願人 日立コンデンサ株式会社 第1 第3図 、@5 第2図 第4
1 to 5 are cross-sectional views of a multimetallic wiring board showing the manufacturing process of the present invention. 1... Insulating substrate, 2... Circuit, 3.4. .. 5.7... Insulating ink, 6.8... Insulating layer. Patent applicant Hitachi Capacitor Co., Ltd. 1 Figure 3, @5 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)両面に回路を形成した絶縁基板の表面に絶縁性イ
ンクを塗布して絶縁層を形成した多属配線板の製造方法
において、絶縁基板の両面に複数回に分けて交互に絶縁
性インクを塗布して所定厚さの絶縁層を形成することを
特徴とする多層配線板の製造方法。
(1) In a method for manufacturing a multi-metal wiring board in which an insulating layer is formed by applying insulating ink to the surface of an insulating substrate on which circuits are formed on both sides, insulating ink is applied alternately to both sides of the insulating substrate in multiple steps. 1. A method for manufacturing a multilayer wiring board, the method comprising: coating an insulating layer with a predetermined thickness.
JP1377889A 1989-01-23 1989-01-23 Manufacture of multi-layer wiring board Pending JPH02194592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1377889A JPH02194592A (en) 1989-01-23 1989-01-23 Manufacture of multi-layer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1377889A JPH02194592A (en) 1989-01-23 1989-01-23 Manufacture of multi-layer wiring board

Publications (1)

Publication Number Publication Date
JPH02194592A true JPH02194592A (en) 1990-08-01

Family

ID=11842702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1377889A Pending JPH02194592A (en) 1989-01-23 1989-01-23 Manufacture of multi-layer wiring board

Country Status (1)

Country Link
JP (1) JPH02194592A (en)

Similar Documents

Publication Publication Date Title
ATE82529T1 (en) PROCESS FOR MANUFACTURING MULTILAYER SEMICONDUCTOR BOARDS.
JPH02194592A (en) Manufacture of multi-layer wiring board
JPS5929160B2 (en) Manufacturing method of wiring board
JPH03171692A (en) Manufacture of organic thick film circuit board
JPH11274720A (en) Manufacture of multilayer-laminated board
JPH0534138Y2 (en)
JPH0388388A (en) Manufacture of multilayer printed wiring board
JP2917837B2 (en) Manufacturing method of ceramic substrate
JPS6049588B2 (en) Manufacturing method of ceramic multilayer printed board
JPH0561799B2 (en)
JPS6244840B2 (en)
JPH04291994A (en) Fabrication of composite ceramic circuit board
JPS63314887A (en) Printed wiring board
JPH10294561A (en) Highly debinderable multilayer wiring board and its manufacturing method
JPH02260599A (en) Manufacture of multilayer board
JP2710430B2 (en) Pattern formation method
JPS5819158B2 (en) Manufacturing method for high-density multilayer wiring board
JPS62236727A (en) Manufacturing method of multilayer substrate for additive method
JPH03280492A (en) Formation of multilayered insulating film
JPS6350861B2 (en)
JPS617698A (en) Method of producing multilayer circuit board
JPH0561797B2 (en)
JP2002271019A (en) Manufacturing method for laminated wiring board
JPS59106190A (en) Method of producing electronic circuit board
JPH02254790A (en) Manufacture of multilayer circuit board