JPH0219499B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a data processing system, and particularly to a data processing system in a control device connected to a channel, equipped with a transmitting/receiving buffer, and controlling a plurality of devices.

Conventional technology and problems Conventionally, the above types of control devices define the transmission and reception buffer according to the maximum amount of data processing of the connected device. In a control device (multi-controller) that connects a mixture of average devices that do not process a large amount of data, if the size of the transmitting and receiving buffer is constant, restrictions will occur in various places, resulting in a lack of flexibility in system design. There is a problem.

Additionally, data transfer in a channel connection is usually much faster than data transfer between a control device and a device, so a send/receive buffer is provided to accumulate data and transfer it all at once. This limits the amount that can be transferred.

OBJECTS OF THE INVENTION The present invention seeks to provide a data processing system that is particularly suitable for multi-controllers and is capable of transmitting and receiving a large amount of data with a relatively small capacity transmitting and receiving buffer.

Structure of the Invention The present invention provides a data processing method in a control device connected between a channel and a plurality of devices with different data throughputs, and equipped with a transmitting/receiving buffer. A plurality of transmitting/receiving buffers are generated, and the unused buffers are used to form an empty buffer chain that is shared by each device, and the currently used buffer chains are used for each device, and the amount of data received is equal to the capacity of the buffers in use. When the buffer is exceeded, a signal is generated, one free buffer is extracted from the free buffer chain, and it is linked after the in-use buffer to continue reception, and when transmitting data, a signal is generated when the in-use buffer becomes empty. Then, the in-use buffer is switched to the subsequent buffer linked to it to continue sending data from the buffer, and the in-use buffer is returned to the empty buffer chain when it becomes empty. This will be explained in detail with reference to.

Embodiment of the invention FIG. 1 is a block diagram of a data processing system, in which 10 is a host computer, CPU is its processor,
CH is a channel. 12 is a control device (multi-controller) to which n devices such as displays 14 and printers 16 are connected. FIG. 2 shows the internal configuration of the control device 12, where 20 is an interface control circuit, 22 is a main control section, 24 is a device control section, and 26 and 30 are DMA (Direct
Memory Access) control unit 28 is n transmitting/receiving buffers. The interface control circuit 20 controls data transfer with the channel CH and activates the main control section 22. The device control unit 24 controls data transmission and reception with the devices 14 and 16.
DMA control circuit 26 has channel CH and buffer 2
Data transmission and reception between 8 and DMA control circuit 30
controls data transmission and reception between the devices 14 and 16 and the buffer 28.

The transmitting/receiving buffer 28 is defined and generated in a part of memory (RAM) that stores programs and the like. In the conventional method, one buffer per device is used, so if the amount of data transferred increases, it cannot be accommodated by the buffer, and if the buffer capacity is made large enough to prevent this, it will consume a large amount of memory capacity. . Therefore, in the present invention, a plurality of buffers of the same size are used so that the transmitting/receiving buffer can be chained at any time. This buffer size may be adjusted to a device that processes a small amount of data, and in this example, it is set to 4KB.
FIG. 3 shows the links of the transmitting and receiving buffers. 28
a, 28b, . . . are each of the above buffers, where a is an empty buffer chain, and b, c are in-use buffer chains generated for devices that are in operation and require buffering. Reference numerals 32, 34, and 36 are tables, and these tables indicate the start address of the buffer at the head of the chain. Each buffer has a link area, and the start address of the subsequent buffer is stored in this area, and a buffer chain is formed by these. Ru.

FIG. 4 shows the main part of the data transfer control system between the channel CH and the buffer 28. DMA control circuit 26
has a memory address register 42, a byte count register 46, and a circuit 48 that successively increments the contents of the register 46 by one. G1 and G2 are AND gates, G3 is OR gate, and S1 is H during transmission.
(high) level, S2 is a signal that becomes H level during reception, S3 is a signal that becomes H level when 1 byte is received, S4 becomes H level when the contents of register 46 becomes 0 (full or empty). This is a signal. Next, the operation of FIG. 4 will be explained with reference to FIG. 5 showing a received data sequence and FIG. 6 showing a transmitted data sequence.

When the control device 12 receives data from the channel CH, as shown in FIG. In response to this, the CPU sends 1 byte of data to the bus out (BUS-OUT) and returns a service out (data modification signal) SVo to the tag out (TAG-OUT) line. The DMA control circuit 26 receives this data through the interface control circuit 20 and the main control section 22, and stores the data in the buffer 28j. The data storage address in this buffer is specified by the main control section 22 by setting it in the memory address register 42 of the DMA control circuit. When the DMA control circuit 26 takes in one piece of data (1 byte), it raises the service-in SVi again to the tag-in line, and sets the service-out to the tag-out line.
When SVo comes out, take in 1 byte data from bus out. The same process is repeated and the data D1, D
2. Sequentially import... The main control unit 22 also stores the length, that is, the number of data that can be stored in the buffer, the complement of 4KB in this example, in the byte count register 46 of the DMA control circuit, and the +1 circuit 48 stores the number of data that can be stored in the buffer in the byte count register 46 of the DMA control circuit. Add 1 to the content.

The reception (writing) is completed as follows. In other words, in response to SVi from the control device after there is no more data to be sent on the channel CH, the channel CH places a CMO (stop instruction) on the tag-out line, and upon receiving this, the control device terminates DMA and returns bus input. Place the channel termination code CE on (BUS-IN) as the device status byte DSB,
And put a stop-in STi on the tag-in line. When the DSB is received from the channel and a service out SVo is received, a data end (end of data reception) DE is instructed to the main control unit 22 to end the data transfer. The main control section 22 notifies the device control section 24 receiving the data end DE of the memory address of the transmission/reception buffer 28j containing the received data, the length of the received data, and the machine number of the device to be output. Upon receiving the data, the device control unit 24 uses the DMA control circuit 30 to output the data to the corresponding device.

These are the processes in a series of data transfers (writing) from the channel to the device, but if the number of receivable bytes specified in the byte count register 46 becomes 0 before the data end DE arrives from the channel CH, it will no longer be possible. The buffer is full and subsequent data cannot be received.

Regarding this problem, in the conventional system, there is a rule that data exceeding the limit value must not be sent due to a limit on the control device side. However, with the advent of devices capable of displaying/printing large amounts of data and the increased capacity of host computers, it is becoming necessary to increase the above-mentioned limit value. The present invention makes it possible to transmit and receive large amounts of data even if the buffer size is the same as or smaller than the conventional one.

In Figure 5b, the content of the byte count register is 0.
Therefore, an example will be shown in which data transfer does not end even if the buffer becomes full. In this case, the present invention uses a data transfer continuation signal DC (Date Continue).
is created and notified to the main control unit. In the circuit shown in Figure 4, the signal DC is the receiving signal S2, and the 1-byte receiving signal S.
3. This occurs because both BCR0 signals S4 are at H level. The signal DC is input to the main control section 22,
As a result, the main control unit knows that the transmitting/receiving buffer 28j is full, and the next transmitting/receiving buffer 28j is
k, and connect it to the interface control unit 20 again.
Notifies the DMA control circuit 26 that data can be requested.

The next sending/receiving buffer is selected from the empty buffers, and as shown in FIG.
28j creates a link, and the address of the first buffer 28a is stored in the table 32. The main control unit 22 sends a data transfer continuation signal DC
When the buffer 28a is received, an empty buffer 28a is found by referring to the table 32, and this is set as the buffer 28k following the buffer 28j. Specifically, the start address of the buffer 28k is written in the link area of the buffer 28j, a plurality of lengths m of the buffer are stored in the byte count register 46, and the addresses of the buffer 28k are sequentially set in the memory address register. do. When this buffer 28k is also full, use the same operation to create the next free buffer 28k.
Link b to buffer 28k. The same applies below. In this way, a link of buffers in use is created, and the addresses of the leading buffers are stored in tables 34 and 36, as shown in FIGS. 3b and 3c.

In an empty buffer chain, when the first buffer is cut out, the address of the next buffer is written into the table 32. Also, when a used buffer becomes used and is released, it is linked to the end of the free buffer chain. Prepare a free buffer link like this, and when the used buffer link becomes full, you can use one buffer from the free buffer link.
If the data is taken in and used as a buffer, data can be transferred without restrictions, and data received earlier can be output to the device during data transfer between channels and control devices, so data processing efficiency is significantly improved. In addition, Batsuhua can be prepared in the required number for the device that requires it.
Compared to a method in which a buffer is fixedly provided for each device, the required buffer capacity can be made smaller, and there is an advantage that data transfer will not be interrupted due to the buffer being full.

When transferring data in the screen memory of a device such as a display to the CPU, the DMA control device 30 first transfers the data in the screen memory to the buffer 28.
j, 28k, and then the DMA control circuit 26
reads the data from the buffer and transfers it to the channel CH. The data transfer between the control device 22 and the channel CH during this read is as shown in Figure 6, and is almost the same as in Figure 5, except that the meaning of each signal is reversed. be. Transmit data is placed on bus-in (BUS-IN). In FIG. 6, a indicates a case where the number of transmitted bytes is smaller than the buffer length, and b indicates a case where the number of transmitted bytes is larger than the buffer length. When the transmitted data exceeds the buffer length, a signal DC is generated,
At this time, the main control section instructs the interface control section 20 and the DMA control circuit 26 to send the next buffer of data. This instruction is the same as for the light. The next buffer can be determined by the address of the link area.

Effects of the Invention As explained above, according to the present invention, a plurality of transmitting/receiving buffers with a capacity suitable for a device that processes a small amount of data is prepared, and data is received using one of the buffers until the buffer becomes full. If so, the next buffer can be linked and used, so data can be transferred to a device that processes a large amount of data without any restrictions, which is extremely effective. In addition, even if there are multiple devices with different types such as large or small processing data, you can select a buffer without being aware of the differences between the types, making it easy to connect new devices to the control device, providing great flexibility and reducing the service life. It can provide long data processing equipment. In addition, since the buffer can be used effectively for each device, the overall memory capacity of the buffer can be reduced. This has the effect of reducing the occupied area as much as possible.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing the configuration of a data processing system to which the present invention is applied, Figs. 2 to 4 are explanatory diagrams and block diagrams showing embodiments of the present invention, and Figs. 5 and 6 are transmission/reception diagrams. It is an explanatory diagram of the procedure in. In the drawing, CH is a channel, 14 and 16 are devices, 28 is a transmission/reception buffer, 12 is a control device,
DC is a signal indicating continuation of data transfer.

Claims (1)

[Scope of Claims] 1. A data processing method in a control device connected between a channel and a plurality of devices with different data throughputs and equipped with a transmitting/receiving buffer, comprising: generate a plurality of such transmitting and receiving buffers, and the unused ones constitute an empty buffer chain that is shared by each device, and the used ones constitute an in-use buffer chain for each device, and the amount of data received is determined by the capacity of the used buffers. A signal is generated when the buffer exceeds the buffer chain, one free buffer is extracted from the free buffer chain, and it is linked after the currently used buffer to continue reception. When transmitting data, a signal is generated when the currently used buffer becomes empty. The data processing method is characterized in that the in-use buffer is switched to a subsequent buffer linked to it to continue sending data from the buffer, and the in-use buffer is returned to an empty buffer chain when it becomes empty.