JPH021952A - Semiconductor integrated circuit in standard cell system - Google Patents

Abstract

PURPOSE:To reduce a wiring region and to contrive the improvement of an integration degree by a method wherein a wiring part for connecting adjacent cells to one another is provided in the interior of a cell. CONSTITUTION:A poly Si wiring part 18 is provided with a wide area part to form a contact part 20 for connecting an output of an inverter circuit 5 to an input terminal on one side of a NOR gate circuit 6 and a first-layer Al wiring layer 11A is connected with the wiring part 18 through this part 20. Moreover, when a connection is performed in the interior of a cell in such a way, vias for connection with a two-layer Al wiring part are omitted because it becomes unnecessary. In addition to that, even when identical signals are individually inputted, a wiring is performed using the poly Si wiring part when the wiring is possible in the interior. By the above method, a wiring region is reduced and a reduction of a wiring capacitance and the speeding-up of the operation of a circuit are contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a standard cell type semiconductor integrated circuit designed to reduce the wiring area.

(Prior art) A standard cell type semiconductor integrated circuit is formed by arranging circuit blocks called standard cells in advance using a computer-based placement program, and automatically designing wiring patterns between these standard cells using a computer-based program processing. be done. This has the advantage that a semiconductor integrated circuit (hereinafter abbreviated as IC) having any circuit function can be manufactured in a short time.

FIG. 4 is a block diagram for explaining a conventional wiring design method using program processing. Standard cells 25 to 2B are arranged in the area bounded by solid lines in the figure. In this standard cell placement program, cells with strong coupling are placed close to each other in consideration of the strength of coupling between cells, and cells are exchanged to avoid local concentration of wiring. will be promoted. In addition, in the wiring program, polysilicon terminals 29 to 35 are placed above and below each cell 25 to 26, and each cell 25 to 28 is
Wiring lines 36 are arranged parallel to the arrangement of the cells 25 to 28, and wiring lines 37 are arranged perpendicular to the arrangement of the cells 25 to 28 and running on the arrangement. In the device process, the wiring 36 is made of a first conductive layer, such as aluminum, and the wiring 37 is made of a second conductive layer, such as aluminum. Each of the wirings 36. is provided on the surface of each cell via an insulating layer.
A contact portion 38 connects the polysilicon terminals 29 to 35 and the wiring 36, and a via (VIA) 39 connects the wiring 36 and the wiring 37. ing.

FIG. 5 is a block diagram of a conventional standard cell type IC in which wiring is performed using the wiring program as described above. In the figure, 40, 41, and 42 are standard cells. Here, for example, when the output of the cell 40 is connected to the human power of the cell 41, the via 39A is provided and the second layer wiring 37 is connected. Then, the wiring 37 and the first layer wiring 36 are connected by providing a 739B outside the cell array, and the first layer wiring 36 and the input polysilicon terminal 43 are connected using the contact portion 38. Wiring processing is performed by connecting the wires.

FIG. 6 is a pattern plan view of a part of a conventional IC based on the standard cell method. The figure shows an example in which the standard cell 40 in FIG. 5 is an inverter circuit. P diffusion regions 44A, 44B and N diffusion regions 45A, 45B are formed on an N-type silicon substrate (not shown), and source/drain regions of P-channel MOS transistor 4B and N-channel MOS transistor 47 are formed, respectively. And polysilicon wiring 48
The drains of both transistors 46 and 47 are commonly connected through a contact portion 49 using a first aluminum wiring layer 50. here,
A via 51 is opened at the output node of this circuit, and then the first layer aluminum wiring 50 is connected to the second layer aluminum wiring via the via 51.

In this way, even when wiring adjacent standard cells, first the first conductive layer is connected to the second conductive layer using a via, and then the wiring is brought out to the outside of the cell and connected to the adjacent cell. I try to do that. Also, depending on the computer program for placement and routing, all placement and routing coordinates may be displayed on a grid (
(virtual grid), and in some cases it may not be possible to wire anywhere other than on that grid. In this case, a large I
When implementing C, the wiring area increases and occupies a larger proportion of the chip area. As a result, the larger the IC becomes, the more it becomes a hindrance to improving the degree of integration, and the increase in wiring capacitance causes an adverse effect on circuit operation.

(Problems to be Solved by the Invention) Conventionally, when performing program wiring processing for standard cells, the wiring area and wiring capacity increase in proportion to the scale of the IC, resulting in problems in terms of high integration and circuit operation. There's a problem.

The present invention has been made in consideration of the above-mentioned circumstances, and its object is to provide a standard cell type semiconductor integrated circuit that can perform wiring processing to improve the degree of integration.

[Structure of the Invention] (Means for Solving the Problems) A standard cell type semiconductor integrated circuit of the present invention has the following features:
It is configured such that wiring for connecting adjacent cells is provided inside the cell.

(Function) Wire and connect using the inside of the standard cell. This aims to reduce the wiring area.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a block diagram of a standard cell type semiconductor integrated circuit according to the present invention. In FIG. 5, each standard cell 1.2.3 is arranged in an area bounded by a solid line. In this invention, when wiring adjacent cells 1.2,
A contact part 4 is provided in the inner region of the cell, and the wiring is connected without being drawn out to the outside.

FIG. 2 is a pattern plan view showing in detail the configuration of the circuit of the above embodiment. Here, it is assumed that the cell 1 is the inverter circuit 5 and the cell 2 is the NOR gate circuit 6. The explanation will be made with reference to FIGS. 3(a) and 3(b), which are equivalent circuits of the FIG. 2 circuit. In the inverter circuit 5, the P diffusion region 7A.

7B and N diffusion regions 8A and 8B are formed, and source/drain regions of each of a P channel MOS transistor and an N channel MOS transistor are formed. The gates of both transistors are constituted by a polysilicon wiring 9, and the drains are commonly connected through a contact portion IO using the first aluminum wiring layer 11A. On the other hand, the NOR gate circuit 6 has a P diffusion region 12A,
12B.

12C and N diffusion regions 13AS13B and 13c are formed, and two P channel MOs are formed as shown in FIG. 3(b).
3) Transistor 14.15 and 2 N-channel MOS
Source and drain regions of transistors 16 and 17 are formed. And transistors 14 and 17
and transistors 15 and 16, and their gate wirings are constructed of polysilicon wirings 18 and 19, as shown in FIG. Further, the wiring formed by the first aluminum wiring layer 11B in FIG. 2 forms a connection point between the drains of the transistor 15 and the transistors 16 and 17 in FIG. 3(b).

By the way, in this invention, the output of the inverter circuit 5 is
To connect to one input terminal of the R gate circuit 6, the second
In the figure, a contact portion 20 is formed by providing a large area portion in the polysilicon wiring 18, and the first aluminum wiring layer 10A is connected to the polysilicon wiring 18 via this contact portion 20. . Further, when the wiring is made inside the cell in this way, the via for connecting to the double-layer aluminum wiring becomes unnecessary and is therefore deleted. In addition, output signals are not only wired internally as input signals of other cells (even if the same signal is input separately, if wiring is possible internally, wire it with polysilicon etc.) good.

By providing and connecting interconnections between adjacent cells inside the cells in this manner, the interconnection area can be reduced. Thereby, the wiring capacitance can be reduced and the circuit operation speed can be increased.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a standard cell type semiconductor integrated circuit in which the wiring area is reduced and the degree of integration is improved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a standard cell type semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a pattern plan view showing the detailed structure of the circuit of the embodiment, and FIG. figure(
a) and (b) are equivalent circuit diagrams of the above pattern plan view, FIGS. 4 and 5 are block diagrams of conventional standard cell type semiconductor integrated circuits, and FIG. 6 is a diagram of one of the configurations of the conventional circuit. FIG. 1.2.3...Standard cell, 4...Contact part. Figure 1 Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (2)

[Claims] (1) A standard cell type semiconductor integrated circuit characterized in that wiring for interconnecting adjacent cells is provided inside the cells. (2) Partially enlarge the dimensions of the polysilicon wiring provided in the cell, form a contact part with the wiring made of a conductive layer in this part, and connect the polysilicon wiring with the conductive layer through this contact part. 2. The standard cell type semiconductor integrated circuit according to claim 1, wherein the standard cell type semiconductor integrated circuit is connected to a wiring line consisting of: