JPH02196968A

JPH02196968A - Oscillator

Info

Publication number: JPH02196968A
Application number: JP1504089A
Authority: JP
Inventors: Masao Kouden; 向殿　政男
Original assignee: Individual
Current assignee: Individual
Priority date: 1989-01-26
Filing date: 1989-01-26
Publication date: 1990-08-03

Abstract

PURPOSE:To set an upper and a lower thresholds by a common resistor by setting the number of amplifiers for determining the threshold to one. CONSTITUTION:When an input signal voltage V is not applied to an input terminal A, a transistor T4 is turned ON, and by its output signal, a transistor 5 is also in a conducting state. In this case, although the input voltage V is not applied, a transistor T6 is in a state of OFF. When the input voltage V is applied, transistors T1, T2 and T3 are turned ON/OFF in the process of T4 : OFF T5 : OFF T6 : ON T4 : ON T5 : ON ... and the circuit is brought to oscillation. Subsequently, as for the threshold of the circuit, when the input voltage V becomes higher than E(R9 + R11 + R12)/R12, the transistor T4 is turned OFF and starts an oscillation, and when the input voltage V is further boosted and exceeds E(R9 + R10)/R10, the transistor T4 becomes the state of OFF and the oscillation stops. That is, two thresholds are determined by the transistor 4, and the threshold can be set by a common resistance R9.

Description

【発明の詳細な説明】（産業上の利用分野）本発明は、たとえばフェールセーフなセンサでアブログ
信号のレベル検定に利用できるコンパレータに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a comparator that can be used, for example, to verify the level of an ablog signal using a fail-safe sensor.

（従来技術）入力レベルの上下にしきい値をもつフェールセーフなレ
ベル検定回路には、たとえば実開昭５７−４７６４号や
実開昭５８−１７５９１号や実開昭６１−＋１６ｆ３１
１　　号公開広報等がある。(Prior art) Fail-safe level verification circuits with threshold values above and below the input level include, for example, Utility Model Application No. 57-4764, Utility Model Application No. 58-17591, and Utility Model Application No. 61-+16f31.
There is No. 1 public information etc.

これらは、たとえば公開広報実開昭５７−４７６４号お
よび実開昭５８−１７５９１号では、いずれも上下２つ
のしきい値が異なる増幅器のコレクタ抵抗で決定され、
かつ構成されるトランジスタが電源電位より高いベース
入力を必要とするために、入力信号は電源電位より高い
入力レベルを必要としていた。また、実開昭６１−１’
７６１７号では、電源電位より高い入力レベルを必ずし
も必要としないが、２つのしきい値をもつ増幅器を必要
とし、かつ、上下のしきい値を定める抵抗器が独立して
いた。For example, in Public Publications No. 57-4764 and No. 58-17591, the upper and lower thresholds are determined by the collector resistance of the amplifier, which is different.
In addition, since the transistors constructed require a base input higher than the power supply potential, the input signal requires an input level higher than the power supply potential. Also, Utsukai Showa 61-1'
No. 7617 does not necessarily require an input level higher than the power supply potential, but requires an amplifier with two thresholds, and separate resistors for determining the upper and lower thresholds.

たとえば、第２図は実開昭５７−４７６４号公開広報に
よる発振回路で、１．２は入力端子、Ｂは出力端子、Ｒ
１，Ｒ２，・・・Ｒ８は抵抗器（抵抗値も同じ記号で表
す）、Ｔ１．Ｔ２．Ｔ３はトランジスタ、Ｅは電源（電
源電位も同じ記号で表す）である０図の回路は、入力端
子１．２に入力電圧が印加されない時、トランジスタＴ
２が導通（ＯＮ）の状態にあり、入力電圧が端子１，２
に印加されると３つのトランジスタにＴ２：０ＦＦ−Ｔ
Ｊ　：０ＦＦ−７１：０Ｎ−Ｔ２　：ＯＮ−’ｒ３：０
Ｎ−Ｔｌ　：０ＦＦ−・・・・・の状態の変化が発生し
て発振する。この発振の条件は入力端子１の入力電位を
Ｖｌ、入力端子２の入力電位を■２とおけば次式で定ま
る。For example, Figure 2 shows an oscillation circuit according to Utility Model Application No. 57-4764, in which 1.2 is an input terminal, B is an output terminal, and R
1, R2, . . . R8 are resistors (resistance values are also represented by the same symbol), T1. T2. T3 is a transistor, and E is a power supply (the power supply potential is also represented by the same symbol).
2 is in a conductive (ON) state, and the input voltage is between terminals 1 and 2.
applied to the three transistors T2:0FF-T
J :0FF-71:0N-T2 :ON-'r3:0
N-Tl: 0FF-... A change in state occurs and oscillation occurs. The conditions for this oscillation are determined by the following equation, assuming that the input potential of the input terminal 1 is Vl and the input potential of the input terminal 2 is 2.

■１〉（Ｒ１＋Ｒ２＋Ｒ３）ＥＲ３（１）０くＶ２く　　（Ｒ６＋Ｒ７）Ｅ　　　　（２）そして
入力端子１．２を共通にして入力電圧をＶ（＝Ｖｌ＝Ｖ
２）とおけば、２つの入力端子のもつ条件の論理積とし
て（すなわち、２つの入力端子をそれぞれもつ増幅器に
よる論理演算による）次の２つのしきい値開で発振する
コンパレータとなる（ウィンドウ・コンパレータと呼ば
れる）。■1〉(R1+R2+R3)E R3(1) 0kuV2ku (R6+R7)E (2) Then, input terminals 1 and 2 are shared and the input voltage is V(=Vl=V
2), it becomes a comparator that oscillates at the opening of the following two thresholds (window (called a comparator).

（Ｒ６＋Ｒ７）ＥＲ７（３）（発明が解決しようとする問題点〉しかしながら、上述の発振器は構成される増幅器やコン
パレータが上下２つのしきい値を定めるために独立して
設けられており、このために、上下のしきい値は独立し
た抵抗器によって定めざるを得ない欠点があった。(R6+R7)E R7(3) (Problem to be solved by the invention) However, in the above-mentioned oscillator, the amplifiers and comparators are provided independently to determine the two upper and lower thresholds, and this Therefore, there was a drawback that the upper and lower threshold values had to be determined by independent resistors.

（問題点を解決する手段）上述する従来の問題点を解決するために、本発明に係る
発振器では、しきい値を定める増幅器（コンパレータ）
を１つにしている。これによって上下しきい値が共通の
抵抗器によって変えることのできる発振器としている。(Means for Solving the Problems) In order to solve the above-mentioned conventional problems, the oscillator according to the present invention uses an amplifier (comparator) that determines the threshold value.
are combined into one. This results in an oscillator whose upper and lower threshold values can be changed by a common resistor.

（作用）本発明の発振器によれば、回路を合理化（簡略化）でき
ると共に、上下のしきい値を共通の抵抗器で調整でき、
かつ１回路が故障した時出力信号が発生しないウィンド
ウ・コンパレータとすることができる。(Function) According to the oscillator of the present invention, the circuit can be rationalized (simplified), and the upper and lower thresholds can be adjusted using a common resistor.
In addition, it can be a window comparator that does not generate an output signal when one circuit fails.

（実施例）第１図は、本発明に係る発振器の実施例を示しＡは入力
端子、Ｂは出力端子、Ｅは電源（電源電位も同じ記号で
示す）、Ｔ４．Ｔ５．Ｔ６はトランジスタ、Ｒ９，ＲＩ
Ｏ，Ｒ１１，Ｒ１２，Ｒ１３、Ｒ１４、Ｒ１５，Ｒ１６
は抵抗器（抵抗値も同じ記号で示す）である、それぞれ
の抵抗器はトランジスタＴ４．Ｔ５．Ｔ６による増幅器
を構成するための抵抗器で、それぞれ、公知の増幅回路
の構成であるので詳細な説明を除＜、１２の回路は以下
のように動作する。入力信号電圧（■とおく）が入力端
子Ａに印加されない時、トランジスタＴ４が導通状Ｂ（
ＯＮ）にあり、この出力信号でトランジスタＴ５も導通
状態にある。このとき入力電圧Ｖは印加されていないが
トランジスタＴ６は非導通（ＯＦＦ）の状態にある。(Embodiment) FIG. 1 shows an embodiment of an oscillator according to the present invention, where A is an input terminal, B is an output terminal, E is a power supply (the power supply potential is also indicated by the same symbol), T4. T5. T6 is a transistor, R9, RI
O, R11, R12, R13, R14, R15, R16
are resistors (resistance values are also indicated by the same symbols), each resistor is connected to a transistor T4. T5. The 12 circuits are resistors for configuring an amplifier using T6, and since they each have the configuration of a known amplifier circuit, a detailed explanation will be omitted.The 12 circuits operate as follows. When the input signal voltage (denoted as ■) is not applied to input terminal A, transistor T4 becomes conductive state B (
ON), and this output signal also makes transistor T5 conductive. At this time, the input voltage V is not applied, but the transistor T6 is in a non-conductive (OFF) state.

−１五入力電圧Ｖが印加されると、トランジスタＴＩ、
Ｔ２．Ｔ３が次の過程でＯＮ、１０ＦＦＩ、て図の回路
は発振する。-15 When an input voltage V is applied, the transistor TI,
T2. When T3 is turned on in the next process and 10FFI is reached, the circuit shown in the figure oscillates.

Ｔ４　：０ＦＦ−Ｔ５：０ＦＦ−Ｔ６：０Ｎ−Ｔ４：０
Ｎ−ｈＴ５：ＯＮ−・・・・この発振条件はＲＩＯ＞Ｒ１１＋Ｒ１２とおくと次式で
決定される。T4:0FF-T5:0FF-T6:0N-T4:0
N-hT5:ON-... This oscillation condition is determined by the following equation when RIO>R11+R12.

（Ｒ９＋Ｒ１１＋Ｒ１２）Ｅ　　　　　　　（４゜図の
回路のしきい値は入力電位■がＥ　（Ｒ９＋Ｒ１１＋Ｒ
１２）／Ｒ１２より高くなるとトランジスタＴ４がＯＦ
Ｆして発振を開始し、さらに入力電圧Ｖが上昇してＥ　
（Ｒ９＋Ｒ１０）、・ＲＩＯを越えると、トランジスタ
Ｔ４はＯＦＦの状態になって、発振は停止する。すなわ
ち、（４）式で示した２つのしきい値はトランジスタＴ
４によって定まり、しきい値は共通の抵抗Ｒ９を有する
。(R9+R11+R12)E (4゜The threshold value of the circuit shown in the diagram is that the input potential ■ is E (R9+R11+R
12) When it becomes higher than /R12, transistor T4 turns off.
F and starts oscillation, the input voltage V further increases and E
When it exceeds (R9+R10), .RIO, the transistor T4 is turned off and oscillation stops. That is, the two threshold values shown in equation (4) are the transistor T.
4 and the threshold has a common resistor R9.

第１図の回路は、トランジスタＴ４．Ｔ５．Ｔ６をＮＰ
Ｎ口ＰＮＰ変換して、電源Ｅを負にすれば、負の入力電
圧で発振する。The circuit of FIG. 1 includes transistors T4. T5. NP T6
If the power supply E is made negative through N-channel PNP conversion, oscillation will occur with a negative input voltage.

また、第１図は点線のブロックＳで示すようにトランジ
スタＴ４．Ｔ５で構成される増幅回路は出力信号として
非反転の出力信号を発生するレベル検出回路の役目を行
っている。したがって、レベル検定回路Ｓの出力信号が
ＯＦＦするレベルをＷとおくと、この場合（４）式は次
式となる。In addition, as shown by a dotted block S in FIG. 1, the transistor T4. The amplifier circuit constituted by T5 serves as a level detection circuit that generates a non-inverted output signal as an output signal. Therefore, if the level at which the output signal of the level verification circuit S turns OFF is set to W, then in this case, equation (4) becomes the following equation.

（発明の効果）以上述べたように、上下のしきい値が１つのレベル検定
回路で定まる発振器としたので、上下のしきい値が共通
の抵抗器で設定できるようになった。(Effects of the Invention) As described above, since the oscillator has the upper and lower thresholds determined by one level verification circuit, the upper and lower thresholds can be set by a common resistor.

[Brief explanation of the drawing]

第１図は本発明に係る実施例、第２図は本発明を説明す
るための従来例である。Ｒ９、ＲＩＯ，Ｒ１１，Ｒ１２・・・抵抗器Ｓニレベル
検定回路（Ｒ９＋Ｒ１１＋Ｒ１２）Ｗ　　　　　　　（５゜第１
図第２図FIG. 1 shows an embodiment according to the present invention, and FIG. 2 shows a conventional example for explaining the present invention. R9, RIO, R11, R12...Resistor S two-level verification circuit (R9+R11+R12) W (5° 1st
Figure 2

Claims

[Claims] 1) a first common emitter transistor amplifier having a collector resistor divided into at least two parts between the input and the power supply ground; and a first common emitter transistor amplifier divided by the collector resistor of the first common emitter transistor amplifier. an oscillator comprising: a level verification circuit that receives as an input signal a voltage obtained by dividing the voltage obtained by dividing the voltage by at least two resistors; and a feedback circuit that feeds back the output signal of the level verification circuit to the base side of the first common-emitter transistor amplifier. . 2) A first common emitter transistor amplifier having a collector resistor divided into at least two parts between the input and the power supply ground, and reducing the voltage divided by the collector resistor of the first common emitter transistor amplifier. a second emitter grounding by a transistor complementary to the transistor of the first transistor amplifier, both having base inputs of a voltage divided by two resistors and having at least two divided collector resistors between the power supply and the power supply ground; a transistor amplifier, a third common emitter transistor amplifier having a base input as a voltage separated by a collector resistor of the second common emitter transistor amplifier and a collector resistor between the third common emitter amplifier and the power supply; An oscillator comprising a feedback circuit whose collector output signal is used as a base input of the first common emitter amplifier.