JPH0219772A - Pulse amplitude data sampling circuit - Google Patents

Abstract

PURPOSE:To make an equipment inexpensive and to permit a high speed processing of a sampling data by providing the sampling data with an effective/ ineffective bit and constituting so as to select the data according to priority. CONSTITUTION:The title circuit is constituted of an input pulse signal 1, A/D converting circuit 2 outputting a digital value 3, comparator 5 outputting a signal detecting signal 6, first DFF 71, first OR gate 81, second-fifth DFF 72-75, first-third resistor 141-143, first-second JKFF 161-162, first-second NOR gate 151-152, second-third OR gate 82-83, reset pulse 19 and pulse amplitude sampling data 17. And, a pulse amplitude data sampling circuit provides the data being sampled with the effective/ineffective bit, by deciding the priority of its bit, the pulse amplitude data wherein a sampling point changes in accordance with a pulse width is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pulse signal specification measuring device, and in particular, for example, radar, E S M (II!1e
Ctronic 5upport Measure) and E CM (Electronic Counter Measure)
This relates to a pulse amplitude data sampling circuit in the field of measurement.[Prior Art] A conventional device of this type is the one shown in FIG. Third
The figure shows pulse amplitude data sampling 1 in which three pieces of data are sampled and pulse amplitude sampling data is selected from among the three pieces of data. In Figure 0, which shows a switching circuit, 1 is an input pulse signal, 2 is an A/D conversion circuit that outputs a digital value 3 every time a clock pulse 18 is applied, and 5I
compares threshold level 4 and digital value 3,
a first comparator outputting a signal detection signal 6;7. 81 is a first D flip-flop that delays the signal detection signal 6 by one clock, and 81 is a first D flip-flop that performs the logical product of the signal detection signal 6 and the output of the D flip-flop 7I and outputs a rising differential pulse 9.
The OR gates 1z and 1s input the rising differential pulse 9, and the second gates output the first delayed rising differential pulse 10 and the second delayed rising differential pulse 11 respectively. 5. 3rd D flip-flop, 14t-14, first to third registers for storing digital value 3; 20, pulse width detection circuit for determining the pulse width of the input signal; 5. 5° is a second comparator that compares the pulse width 23 and the first comparison data 21, 5° is a third comparator that compares the pulse width 23 and the second comparison data 22, and 22 is the second comparator.
Comparator 5□ and third comparator 5, NAN that takes the logical OR of the output
D gate, 24 is the third comparator 5. 82 is a second OR gate that ANDs the outputs of the second comparator 5□ and the inverting gate 24, and 17 is pulse amplitude sampling data that is the output of the first to third registers.

Next, the operation will be explained with reference to FIG.

When input pulse signal 1 is input to A/D conversion circuit 2, digital value 3 is obtained every time clock pulse 18 is applied. First comparator5. Then, a comparison is made to see if the digital value 3 exceeds the threshold level 4, noise and signal are distinguished, and a signal detection signal 6 is detected. The signal detection signal 6 is delayed by one clock in the first D flip-flop 7, and is inputted to the first OR gate 8I to generate a rising differential pulse 9. When the rising differential pulse 9 is output to the enable terminal of the first register 141, the digital value 3 when it exceeds the threshold level 4 for the first time becomes the second digital value.
Stored in register 14□.

Further, the rising differential pulse 9 is applied for 1 clock, 2 clocks, 2nd . It is delayed by the third D flip-flops 7□ and 73, and the output of the first . Second delayed rising differential pulse 10
．． 11 respectively as the second. 14□, 14. of the third register.
When output to the enable terminal of the second register 14□, the second clock from the pulse rise, the third register
The digital value 3 of the third clock is stored in . After the pulse input is completed, the pulse width detection circuit 20 detects the pulse width 2.
3 is detected, for example, the first comparison data 21 is changed to “3”.
”, and the second comparison data is set to “5”, if the detected pulse width is 2 or less, the second comparison data is set to “5”. Third comparator 5
□, 5. The output of the NAND gate 25 becomes invalid, the output of the NAND gate 25 becomes valid, and the data of the first register 141 is output as the pulse amplitude sampling data 17. Further, when the pulse width is 3 or more and 4 or less, the OR gate 8t is enabled and the data in the second register 14□ is valid, and when the pulse width is 5 or more, the third register 14. data is output as pulse amplitude sampling data 17, respectively.

In summary, pulse width = 1 or 2 1st clock data Pulse width = 3 or 4 2nd clock data Pulse width = 5 or more The 3rd clock data becomes the pulse amplitude sampling data 17.

[Problem to be solved by the invention]

Conventional pulse amplitude data sampling circuits are configured as described above, which requires a large number of comparators, resulting in a large circuit size, and furthermore, the sampled data cannot be finalized until after the pulse input has finished and the pulse width has been detected. Without,
There were problems such as a long processing time.

This invention was made to solve the above problems, and it is possible to obtain a pulse amplitude data sampling circuit that is inexpensive, compact, and capable of high-speed processing by using a comparator only in the signal detection circuit. purpose.

[Means to solve the problem]

The pulse amplitude data sampling circuit according to the present invention reduces the number of required comparators to one by providing a data valid bit, so that the pulse amplitude sampling data can be determined without waiting for the end of the input pulse.・ [Operation] The pulse amplitude data sampling circuit in this invention adds a valid/invalid bit to the sampled data,
By determining the priority of the bits, pulse amplitude data whose sampling point changes depending on the pulse width is obtained.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a pulse amplitude data sampling circuit according to an embodiment of the present invention. Similar to FIG. This is a data sampling circuit.

In FIG. 1, the same reference numerals as in FIG. 3 indicate the same or equivalent parts, 1 is an input pulse signal, 2 is an A/D conversion circuit that outputs a digital value 3 every time a clock pulse 18 is applied,
5 is a comparator that compares the digital value 3 with a threshold level and outputs a signal detection signal 6; 7. is signal detection signal 6
a first D flip-flop that delays by one clock;
Reference numeral 81 denotes a first circuit which performs the logical product of the signal detection signal 6 and the output of the first D flip-flop 71 and outputs a rising differential pulse 9.
OR gate, 7. ~7. inputs the rising differential pulse 9, and inputs the first to fourth delayed rising differential pulses 10 to 13, respectively.
2nd to 5th D flip-flops, 141 to 1, which output
4. are the first to third registers that store the digital value 3,
16. ．． 16□ is the second. The first . 2nd J- is a flip-flop, 15+, 15g is 2nd. The first . The second NOR gate, 8□, 83 is the first. 2nd J- flip-flop 16. ．． Take the AND of the outputs of 16□ and 1. Second register 14. ．． The second one controls the output of 14□. The third OR gate 19 is connected to the first and second J- flip-flops 16. ．． 162, a reset pulse 17 resets the first to third registers 14. ~14. This is the pulse amplitude sampling data that is the output of .

Next, the operation will be explained with reference to FIG.

When input pulse signal 1 is input to A/D conversion circuit 2, digital value 3 is obtained every time clock pulse 18 is applied. The comparator 5 compares whether the digital value 3 exceeds the threshold level 4, distinguishes between noise and signal, and outputs a signal detection signal 6. The first D flip-flop 7I delays the signal detection signal 6 by one clock,
A rising differential pulse 9 is generated by ANDing the signal detection signal 6 with the OR gate 8I. Rising differential pulse 9
No. 14. When the digital value 3 is output to the enable terminal of the register 14, the digital value 3 when the threshold level 14 is exceeded for the first time is stored in the register 14. Further, the rising differential pulse 9 is applied for one clock, two clocks, and the second clock. The output of the first . Second delayed rising differential pulse 10.1
1 and 2nd respectively. When outputting to the enable terminals of the third register 14□ and 14°, the second register 14□ receives the second clock from the pulse rise, and the third register 143 receives the third clock.
The digital value of the clock is stored. 3D flip-flop 7. When the second delayed rising differential pulse 11, which is the output of This shows that the above is true. Similarly, when the fourth delayed rising differential pulse 13 and the signal detection signal 6 are ANDed by the second NOR gate 152, the output shows that the pulse width is 5 or more.

1st. Second NOR gate 15, . With the output of 15□,
If the pulse width is 3 or more, the first J- is connected to the flip-flop 16. is 5 or more, the first. Flip-flop 16, . 16□ are set respectively. Second
Flip-flop to J-16. is set, the data of the third register 143 is output as the pulse amplitude sampling data 17, the flip-flop 161 is set to the first J-, and the flip-flop 16□ is set to the second J-.
is in the reset state, the third OR gate 8. becomes valid, the data in the second register 14□ is output as the pulse amplitude sampling data 17, and the data in the second register 14□ is output as the pulse amplitude sampling data 17. 2nd J- flip-flop 16. ．． 16□ are both in the reset state, the second OR gate 8□ is enabled and the second register 14,
data is output as pulse amplitude sampling data 17. Therefore, pulse width -1 or 2 1st clock data pulse width = 3 or 4 2nd clock data pulse width = 5 or more The third clock data becomes the pulse amplitude sampling data 17.

In the above embodiment, the flip-flop 16.
was used as an element for storing a pulse width of 3 or more, but in the present invention, a flip-flop t6. can also be used as an element for storing only pulse width = 3 or 4, and the second embodiment of the present invention in this way is described as a second embodiment of the present invention.
As shown in the figure. As shown in the figure, the output of the second NOR gate 15t and the reset pulse 19 are ORed by the OR gate 8. Then, the first J- flip-flop 16. However, if the output is made to the terminal, the first flip-flop 161 will be reset when the pulse width is 5 or more, and this will cause the first flip-flop 161 to be output to the terminal.
- The flip-flop 161 is set only when the pulse width is 3 or 4, and the data in the second register 142 is output as the pulse amplitude sampling data 17. The other operations are exactly the same as in the previous embodiment.

In FIG. 2, numerals 1 to 18 are the same parts as in the first embodiment shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, sampling data is provided with valid/invalid bits, and data is selected by taking priority of the valid/invalid bits, so that only one comparator is required, and the device This can be done at low cost, and since the pulse amplitude sampling data is determined without having to obtain the calculation result for determining the pulse width after the end of the input pulse, the processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a pulse amplitude data sampling circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional pulse amplitude data sampling circuit. It is a circuit diagram. In the figure, l is an input pulse signal, 2 is an A/D conversion circuit,
3 is a digital value 3.4 is a threshold level, 5 is a comparator, 6 is a signal detection signal, 71 is a first D flip-flop constituting a rising differential pulse generating means, 7□, 7
．． ．． 7. ．． 7s is the first to fourth D flip-flops that constitute the first to fourth delayed rising differential pulse generating means, 8 is the first OR gate that together with the first D flip-flop constitutes the rising differential pulse generating means, and 9 is the rising edge Differential pulses 10-13 are the first to fourth delayed rising differential pulses, l41+ 14g, 14s are the first to third registers, 15+, LL are the first to fourth delayed rising differential pulses, and 15+ and LL are the first to fourth delayed rising differential pulses, respectively, which constitute an AND gate. The second NOR gate 82,8 constitutes a logical OR gate. The third OR gate, 161, 168, constitutes the valid/invalid storage means. The second J- is a flip-flop, 17 is pulse amplitude sampling data, 18 is a clock pulse, and 19 is a reset pulse. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A circuit that samples pulse amplitude data by changing the sampling time from the pulse rise depending on the pulse length, and an A/D conversion circuit that converts the input pulse signal from an analog value to a digital value, and this conversion a comparator that compares the amplitude value of the digital value with a threshold level and creates a signal detection signal; a rising differential pulse creating means that creates a differential pulse of the rising edge of the signal detection signal; a delayed rising differential pulse generating means for generating the first to fourth delayed rising differential pulses; a first register storing the digital value A/D converted by the rising differential pulse; and the second and third delayed differential pulses. second and third registers that store the digital values according to the rising differential pulse; and a first register that stores whether the data stored in the second and third registers is valid.
, a second valid/invalid storage means, first and second AND gates for ANDing the second and fourth delayed rising differential pulses and the signal detection signal, and the first and second valid/invalid second and third registers that take the logical sum of the outputs of the invalid storage means and control the outputs of the first and second registers;
A pulse amplitude data sampling circuit comprising: an OR gate;