JPH021982A - Mis type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make the fluctuation of a threshold voltage due to the exposure to radiation small by a method wherein a gate insulating film, provided between a semiconductor substrate and a gate electrode, is formed into a two-layered structure composed of a thermal oxide film and a BPSG film. CONSTITUTION:A field oxide film 2 and a thermally oxidized film 4 are formed on a P-type silicon substrate 1 thought a selective oxidation and a thermal oxidation method. After that, a BPSG film 5a and a poly silicon film 6A are successively grown on the whole face through a CVD method. And, after phosphorus has been thermally diffused into the polysilicon film 6A making use of a photolithography technology, the polysilicon film 6A and the BPSG film 5A are formed into patterns for the formation of a gate electrode 6 and a BPSG film 5 thereunder. By this structure, movable positive charges reached to an interface between the thermal oxide film 4 and the silicon substrate 1 are remarkably reduced in number and the formation of a interface level is reduced, so that a threshold voltage can be restrained from fluctuating.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MIS type (insulated gate type) semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having radiation resistance.

[Conventional technology]

Generally, in MIS semiconductor integrated circuit devices, positive charges are accumulated in the oxide film, especially the gate oxide film, due to exposure to ionizing radiation (T-rays, X-rays, electron beams), etc., and the interface between the oxide film and the silicon boundary is As the position increases, the characteristics change. Therefore, for equipment used in radiation exposure environments such as artificial satellites and nuclear reactor inspection robots, low power consumption
It has become difficult to apply IS type semiconductor integrated circuit devices.

Conventionally, therefore, countermeasures have been taken, such as lowering the temperature of the oxide film forming process and annealing in a nitrogen atmosphere after forming the oxide film.

[Problem to be solved by the invention]

With the conventional countermeasures described above, it is difficult to suppress the positive charges accumulated in the gate oxide film and the generation of interface states when exposed to radiation, and the The threshold voltage will be changed significantly. For example, in an operational amplifier configured using this MISFET, the operating point is moved due to fluctuations in threshold voltage, resulting in a narrow dynamic range and a problem that its use is restricted.

SUMMARY OF THE INVENTION An object of the present invention is to provide an MIS type semiconductor integrated circuit device that can reduce fluctuations in threshold voltage due to radiation exposure.

[Means to solve the problem]

In the Mis-type semiconductor integrated circuit device of the present invention, the gate insulating film provided between the semiconductor substrate and the gate electrode has a two-layer structure of a thermal oxide film and a BPSG (boron phosphorus glass) film.

[Effect]

In the above-mentioned configuration, the mobile positive charges generated in the thermal oxide film due to radiation exposure are recombined and annihilated or captured and immobilized by the recombination centers and capture centers in the BPSG film, and the mobile positive charges are generated in the thermal oxide film. This suppresses the movement of the metal to the interface between the semiconductor substrate and the semiconductor substrate, thereby reducing the formation of interface states.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

In the figure, 1 is a P-type silicon substrate, an active region is defined by a Fifield oxide film 2, and a high concentration N-type diffusion layer 3 is formed on the main surface of the silicon substrate 1 in this active region to serve as a source. It constitutes the drain region. Further, a thermal oxide film 4 is formed in the active region, and a BPSG film 5 is formed on this thermal oxide film 4, and these thermal oxide films 4 and BPSG
A gate electrode 6 is formed of conductive polysilicon using the two-layer structure of the film 5 as a gate insulating film.

The sight on this gate electrode 6 is breathtaking! A wiring conductor 8 is formed which is electrically connected to the source/drain region 3 through a contact hole formed therein. Furthermore, a passivation film 9 is formed on this.

A part of the manufacturing process of a MIS type semiconductor integrated circuit with this configuration,
That is, a method for forming the gate insulating films 4 and 5 and the gate electrode 6 will be explained using FIGS. 2(a) to 2(c).

First, as shown in FIG. 2(a), a field oxide film 2 and a thermal oxide film 4 are formed on a P-type silicon substrate 1 by a selective oxidation method and a thermal oxidation method.

Next, as shown in the same figure (b), B is applied to the entire surface by CVD method.
A PSG film 5A and a polysilicon film 6A are sequentially grown.

After thermally diffusing phosphorus into the polysilicon film 6A, the polysilicon film 6A and the BPSG film 5A are patterned using photolithography as shown in FIG. BPSG film 5 is formed.

According to this configuration, when exposed to radiation, the thermal oxide film 4
A large number of mobile positive charges are generated in the thermal oxide film 4, but since the BPSG film 5 adjacent to the thermal oxide film 4 contains many recombination centers and capture centers, these mobile positive charges are recombined and annihilated.
Or captured and immobilized. Therefore, the thermal oxide film 4
The number of mobile positive charges reaching the interface between the silicon substrate 1 and the silicon substrate 1 is drastically reduced, and the formation of interface states is reduced. This results in
Fluctuations in threshold voltage can be suppressed, and even when this MIS type semiconductor integrated circuit device is used as an operational amplifier, a circuit with a wide dynamic range can be constructed.

〔Effect of the invention〕

As explained above, in the present invention, since the gate insulating film has a two-layer structure of a thermal oxide film and a BPSG film, the movable positive charges generated in the thermal oxide film due to radiation exposure are transferred to the BPSG film.
Recombination annihilation or capture immobilization by recombination centers and capture centers in the film suppresses the movement of the mobile positive charges to the interface between the thermal oxide film and the semiconductor substrate, thereby reducing the formation of interface units, MI with excellent radiation accuracy by suppressing threshold fluctuations
An S-type semiconductor integrated circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of one embodiment of the present invention, and FIGS. 2(a) to 2(c) are longitudinal sectional views of a part of the process for manufacturing the structure shown in FIG. l... P-type silicon substrate, 2... field oxide film, 3... source/drain region, 4... thermal oxide film,
5... BPSG film, 6... Gate electrode, 7... Interlayer insulating film, 8... Wiring conductor, 9... Passivation film. Figure 1 9P, 7N-2/Wo, Present 3 Nno L-Ray/4 people 1 P Senoko 2 Lick 2nd

Claims (1)

[Claims] 1. An MIS type semiconductor integrated circuit device in which a gate electrode is formed on a semiconductor substrate via a gate insulating film, characterized in that the gate insulating film has a two-layer structure of a thermal oxide film and boron phosphorus glass. MIS type semiconductor integrated circuit device.