JPH0219933A - Memory circuit controller - Google Patents

Abstract

PURPOSE:To store a program into a memory area of the RAM of a memory circuit and to simplify a debugging job by selecting the memory area of the RAM instead of a memory area of the ROM of the memory circuit in a test mode. CONSTITUTION:A state holding circuit 14 outputs a state signal ROMS in a set state. Then a memory circuit control part 12 which inputted the signal ROMS and an address decoding signal received from an address decoding part 11 outputs the selection signals of a normal mode for selection of a ROM 21 of a memory circuit 20 and the memory areas of RAM 22-24. At the same time, the circuit 14 turns on a resetting switch 32 for input of a resetting signal and outputs a state signal RAMS in a reset state. While the part 12 outputs the selection signals for selection of the ROM 21 and the memory areas of the RAM 22-24 in a mode different from a normal mode. Thus a program to be debugged is stored in the RAM 24 instead of the ROM 21 and therefore a debugging job is simplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a storage circuit control device in equipment equipped with a microprocessor, and in particular to a device that can easily debug and verify software of a ROM, which is a storage circuit. The present invention relates to a storage circuit control device.

[Conventional technology]

FIG. 7 is a block diagram showing an example of a conventional memory circuit control device in a typical 8-bit microprocessor system. Reference numeral 1 denotes a storage circuit control device, which inputs an address control ROM circuit 2 connected to an address bus AB, its output signals, and various control signals (for example, read/write signals, etc.) from a microprocessor to control the storage circuit. The storage circuit control circuit 30 has two circuits that output a selection signal for selecting four memory areas. Furthermore, the memory circuit 4 is
Data is input and output to and from the data bus DB via the path buffer 5.

FIG. 8 is a memory map of the memory circuit 4.

In this figure, addresses oooo to 7FFF are mainly program areas for storing data such as programs, while addresses 8000 to FFFF are used to store data other than programs, such as image signal data and control information data. This is a data storage area for Further, in the program area, addresses 0000 to IFFF are a read-only ROM area, and addresses 2000 to 7FFF are a readable and writable loss area. Note that the program area shown in FIG. 8, addresses oooo to 7FFF, is 8k.
Each B will be called base bank θ~3.

In FIG. 7, the address control ROM circuit 2 is connected to the top 10 of the 16 address lines of the address bus AB, and in order to select each memory area of the storage circuit 4 described above, the address control ROM circuit 2 is connected to the following 581 Outputs similar signals.

(a) ROM area (base puncture O) selection signal (b)
RAM area (base bank 1) selection signal (c) RA
M area (base bank 2) selection signal (d) RAM area (base bank 3) selection signal (d) ROM/RA
M area identification signal Figure 9 shows these signals (-) to (,).
A correspondence diagram between and addresses is shown. In this figure, each selection signal (,) to (
d) is rHJ. In addition, the ROM/RAM area identification signal (,) is the ROM area selection signal (,) rHJ
rHJ is used to identify the ROM area only where . In addition, in this figure, the RO of (f)
The M/RAM area identification signal will be explained later in the test operation.

By inputting the five types of signals explained above and each control signal of the microprocessor (read signal RD, write signal WR, memory request signal MREQ, etc.) to the memory circuit control circuit 3, the memory circuit control circuit 3 Predetermined control actions (data input/output, etc.) are performed on each memory area of the storage circuit 4.

By the way, since the program stored in the ROM area of the normal storage circuit 4 has not been verified by debugging in its initial state, there is no guarantee that the program will operate normally. Therefore, verification work by debugging is required, and in this case, it is usually necessary to secure a RAM area that operates at the same address as the ROM area mentioned above in order to store the program to be debugged in RAM and debug it. Become. Before explaining how to secure and control this RAM area, the control normally performed on each memory area by the storage circuit control circuit 3 will be explained for each memory area.

(1) ROM area (addresses oooo to I FFF': base bank 0) This area is a read-only area of the memory circuit 4, and the memory circuit control circuit 3 uses the ROM area (base bank 0) input from the address control ROM circuit 2. Bank O) Selection signal and ROM
/RAM The memory area is identified by the signal for each fit, and the readout of the memory area is controlled in accordance with the memory request signal MERQ and read signal RD input from the microprocessor.

(21 RAM area (addresses 2000 to 7FFF: base banks 1 to 3) This area is the read and write area of the memory circuit 4, and the memory circuit control circuit 3 is the address control ROM circuit 2
A memory area is identified by a RAM area (base bank 1 to 3) selection signal and a ROM/RAM identification signal input from the microprocessor, and a memory request signal MERQ input from the microprocessor.

Reading and writing to the memory area is controlled according to the combination of read signal RD and write signal WR.

The above is the control for the memory area in the normal case. Next, control over the memory area when debugging, that is, during testing, will be explained.

At the time of testing, in order to store the program to be debugged, a new RAM area with a memory capacity equivalent to the aforementioned ROM area (base bank O) is created, and the ROM/RAM area identification signal ( f
ROM/R that is rLJ corresponding to all addresses as shown in ), that is, selects the RAM area.
An address control ROM circuit 2 that outputs an AM identification signal was newly provided. In this way, the RAM area for storing the program to be debugged is secured and controlled.

[Problem to be solved by the invention]

In the conventional storage circuit control device described above, since the address control ROM circuit 2 is constituted by a ROM, there are the following problems.

(1) The address control ROM circuit 2 must be of type 28, including one for normal use and one for debugging.

(2) Since the address control ROM circuit 2 is a black box in terms of circuit notation, the logical contents written in it cannot be understood as it is, so it is necessary to write the logical contents on the time chart.

(3) Since it is necessary to write logical contents into this address control ROM circuit 2, there is a possibility that erroneous contents may be written due to a writing error or the like.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a storage circuit control device that can control a storage circuit in normal times and during debugging with a simple configuration and clear logic.

[Means to solve the problem]

The storage circuit control device of the present invention selects designated memory areas of ROM and RAM located at different addresses, and is comprised of the following.

(a) An address decoder section that decodes an address signal and outputs an address decoded signal.

(b) A device that maintains two stable states, such as a so-called flip-flop circuit, and inputs a set signal generated at the time of initial reset by a power-on reset of a microprocessor system or a reset by a manual reset switch, etc. Set state (
A state holding circuit that enters a reset state (a second stable state) when a reset signal is input from the outside and outputs state signals corresponding to these two types of stable states.

(c) A storage circuit control unit that outputs a selection signal for selecting a designated memory area of the ROM and RAM in accordance with the address decode signal and the status signal.

[Effect]

When the state holding circuit receives a set signal at the time of initial reset, it enters a set state and outputs a state signal corresponding to this state. The memory circuit control section that receives this status signal and address decode signal inputs the R
Outputs a normal mode selection signal for selecting memory areas of OM and RAM.

Furthermore, when a reset signal is input from the outside, the state holding circuit enters a reset state, and outputs a state signal corresponding to this state. The storage circuit control section which receives the state signal and the address decode signal outputs a test mode selection signal for selecting a memory area of the ROM and RAM different from the normal mode, corresponding to the designated address.

As a result, the storage circuit control section can select a ROM memory area in the normal mode and a RAM memory area in the test mode, corresponding to the specified address.

〔Example〕

Next, embodiments of the invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. 1
1 is an address decode unit, which is connected to an address bus (not shown) and receives a decode signal Y.

~Y3 is output. Reference numeral 13 denotes a set pulse generator, which repeatedly outputs an "L" pulse signal at a constant cycle when the input is rLJ, and stops outputting the rLJ pulse signal when the input reaches rHJ, thereby generating the pulse signal described later. This circuit operates to prevent malfunction when the state of the 7-lip flop circuit 14 is reversed due to noise.

A reset pulse generating circuit 31 outputs an "L" pulse signal when the reset switch 32 is turned on and the rLJ signal is input to this circuit. Reference numeral 14 denotes a flip-flop circuit (hereinafter referred to as an F/F circuit), and the output of the set pulse generating section 13 is applied to the set human power S, and the output of the reset pulse generating circuit 31 is applied to the reset input R. It has become. Further, the two outputs Q and Q of the F/F circuit 14 are contradictory to each other, and the output Q is outputted as the ROkiS signal and the output Q is outputted as the RAM5 signal. 12 is a memory circuit control unit, which is a combinational circuit made up of a combination of logic elements;
By manually inputting the 80M5 signal and the RAM5 signal, and inputting the decoded signals Y and %Y3,
Selection signals 12A to 1 for selecting the OM area and RAM area
Output 2D. 20 is a memory circuit; ROM area 21;
RAM areas 22 to 24) correspond to base banks 0 to 3, respectively. In this embodiment, each base bank has a memory capacity of 8 bytes.

Next, the operation will be explained.

First, a normal mode in which normal operations are performed will be described. When the power is turned on, a power-on reset works like a general microcomputer system, and the F
The /F circuit 14 is applied with a set input (not shown) and enters the set state, and the output Q becomes "H" and the output Q becomes rLJ, so the 80M5 signal becomes rHJ and the RAM5 signal becomes rLJ.
It will be output to the storage circuit control section 12 in this state.

In addition, the set pulse generator 13 receives this RAM5 signal (
After inputting "LJ)," 140 sets of F/F circuits are set manually.
The output of the rLJ repetitive pulse signal is started.

Therefore, the output of the F/F circuit 14 becomes set state, that is, when Q is held at "H" and Q is held at rLJ state, it becomes K.

Next, a waveform diagram of input/output signals in the 1-memory circuit control section 12 is shown in FIG. As shown in this figure, in the normal mode, the 80M5 signal is rHJ, the RAM5 signal is II,]
In this state, the storage circuit control unit 12 stores the selection signals 12A to 12D according to the decode signal stones ~Q applied from the address decoding unit 11 by the action of the combinational circuit. Output to the circuit 20. As a result, RO
M area 21, RAM areas 22-24. That is, base banks 0 to 3 are selected. In addition, as shown in FIG. 2, the decode signal yo-Y3 and the selection signals 12A to
12D is a negative logic signal.

FIG. 3(A) shows a memory map in normal mode.

The ROM area (base bank 0) is located at addresses oooo to IFFF, and the RA area is located at addresses 2000 to 7FFF.
M areas (base banks 1 to 3) are arranged.

Next, if the program stored in the ROM area 21 of the storage circuit 20 is before debugging, and this program is stored in the RAM area 24 instead of the ROM area 21 and the program is to be debugged, that is, a test is performed. The operation of the mode will be explained.

However, at this time, it is assumed that this system has already been powered on and this storage circuit control device is in the aforementioned normal mode. In FIG. 1, when the reset switch 32 is turned on and the signal [LJ is input to the reset pulse generation circuit 31, the reset pulse generation circuit 31 outputs the pulse signal rLJ to the reset input R of the F/F circuit 14. Therefore, the output of the F/F circuit 14 is in a reset state, that is, Q is "L" and Q is in rHJ state, so 80M
The RAM5 signal is output to the storage circuit controller 12 in the "L" state and the RAM5 signal in the rHJ state. Further, after receiving this RAM5 signal ([HJ), the set pulse generator 13 stops the "L" repetitive pulse signal that has been outputted to the set human power S of the F/F circuit 14 so far. Therefore, the output of the F/F circuit 14 is held in a reset state, that is, Q is maintained at rLJ and Q is maintained at rHJ.

Next, a waveform diagram of the input/output signals in the storage circuit control section 12 at this time is shown in FIG. 2 as in the normal mode. As shown in this figure, in the test mode, the 80M5 signal is
The LJ and RAM5 signals are held in the rHJ state, and in this state, the memory circuit control unit 12 outputs the selection signal according to the decode signal Yo-Y3 applied from the address decoder 11 by the action of the combinational circuit. is outputting. In this case, unlike in the test mode described above, the selection signal 12D is the same as <Y with respect to the decode signal 7'O.
3, 12A is output respectively. As a result, the RAM area 24 (base bank 3) is selected in response to the decode signal Yo, and the ROM area 21 (pace bank O) is selected in response to the same <Ys. To explain this using the memory map shown in FIG. 3(B), the address oo
A RAM area (pace bank 3) is located at addresses oo to 1FFF, a ROM area (pace bank O) is located at addresses 6000 to 7FFF, and a ROM area (pace bank O) is located at addresses 6000 to 7FFF.
A RAM area (pace banks 1 and 2) is arranged at address FFF. Tsumushi, ROM in normal mode
area (base bank 0) and RAM area (pace bank 3).
) are exchanged and placed, then K becomes.

This makes it possible to perform debugging by storing the program to be debugged in the RAM area (base bank 3) instead of the ROM area (base bank 0).

In addition, in the case of this embodiment, the ROM is
Since the RAM area (base bank 3) is used in place of the area (pace bank O), this RAM area (base bank 3) is originally an empty area, that is, when the program 2 is in normal mode. It must be an unwritten area. If at this time a program is written in the RAM area (base byte 3), it is necessary to expand the RAM area as shown in the following second embodiment.

FIG. 4 is a configuration diagram showing a second embodiment of the present invention.
The same symbols as in the figure indicate corresponding parts. FIG. 5 is a waveform diagram of input/output signals in the memory circuit control unit 12 of the same embodiment;
The figure shows a memory map of the storage circuit 20 in the same embodiment. The same embodiment will be described below with reference to these drawings, but the explanation of parts that overlap with the first embodiment will be omitted.

In FIG. 4, reference numeral 25 denotes an additional RAM area, which is used only in the test mode. Further, this additional RAM area 25 has the same capacity as the other RAM areas. 3
0 is an additional RAM selection circuit which outputs a selection signal 12E for selecting the additional RAM area 25.

Next, the operation will be explained.

First, the operation in normal mode will be explained. in this case,
As shown in Figure 5, the iCROM5 signal is rHJ, RAM5
While the signal is held in the rLJ state, the memory circuit control section 12 responds to the decode signals y, -y, applied from the address decoding section 11 through the action of its combination circuit and the RAM selection circuit 30. selection signals 12A to 12
D (excluding 12E) is output to the storage circuit 20. As a result, R
OM area 21, RAM areas 22-24. That is, base banks 0 to 3 are selected. In this case, as shown in FIG. 6(A), the contents of the memory map are
This is the same as in the embodiment.

Next, the operation in test mode will be explained. in this case,
As shown in Fig. 5, the K ROM5 signal is “L” and the RAM5
° The signal is held in the "H" state, and in this state, the memory circuit control section 12 uses the combination circuit and the additional RAM selection circuit 30 to select the decode signal stone ~Y3 applied from the address decoding section 11. A selection signal is output accordingly. In this case, unlike in the test mode described above, the selection signal 12K is output in response to the decode signal yo, so the additional RAM area 25 is selected. To explain this using the memory map shown in FIG. 6(B), the additional RAM area 2 is located at addresses 0000-IFFF.
5 is placed, and R is placed at addresses 2000 to 7FFF.
AM areas (base banks 1 to 3) are arranged. First, if the additional RAM area 25 is arranged in place of the ROM area 21 (base bank 0) in the normal mode, then K is obtained.

This allows the program to be debugged to be added to the RAM area instead of the ROM area 21 (base bank 0).
It becomes possible to store the data in the area 25 and perform debugging work, and it becomes possible to secure the same capacity of the RAM area that can be used in the normal mode as in the normal mode.

〔Effect of the invention〕

As explained above, when selecting a memory area of a storage circuit corresponding to a designated address, the storage circuit control device of the present invention selects a ROM memory area in the normal mode, and selects a ROM memory area in the test mode. It is possible to select a RAM memory area as a substitute for this ROM memory area.

Therefore, it is possible to store the program in the memory area of the RAM and perform debugging work.

Therefore, the two types of address control ROMs conventionally used
Since no circuit is required, there is no need to create a time chart showing the logical contents of the control ROM circuit, and there is no need to worry about writing errors to this ROM circuit, making it possible to easily debug programs. have an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a waveform diagram of input/output signals in the storage circuit control section of the same embodiment, FIG. 3 is a memory map of the same embodiment, and FIG. A configuration diagram showing the second embodiment, FIG. 5 is a waveform diagram of input/output signals in the storage circuit control section of the same embodiment, FIG. 6 is a memory map in the same embodiment, and FIG. 7 is a diagram of the conventional storage circuit control device. A configuration diagram showing an example, FIG. 8 is a memory map of the same example, and FIG. 9 is a correspondence diagram of signals and addresses in the same example. 11...Address decoder section, 12...Storage circuit control section, 13...Set pulse generation section, 14φ.
φφ7 lip-flop circuit, 31, φ, reset pulse generation circuit, 30, memory circuit.

Claims (1)

[Scope of Claims] A storage circuit control device that is provided in a microprocessor system that uses ROM and RAM as storage circuits and outputs a selection signal that selects designated memory areas of the ROM and RAM that are arranged at different addresses. , an address decoder section that decodes an address signal and outputs an address decode signal; and a first stable state when a set signal generated at the time of initial reset of the microprocessor system is input, and a reset signal is input from the outside. second in case
and a storage circuit control section that outputs the selection signal in response to the address decode signal and the state signal. Characteristic memory circuit control device.