JPH0219959A - data processing system - Google Patents

Abstract

PURPOSE:To improve the data transfer throughput by dividing the inside of a data transfer device into plural units and making each unit perform the transfer of data via the data transfer device which works with the same clock as that of a data processor which performs the transfer of data. CONSTITUTION:A data transfer device 20 set between the data processors 1 and 3 having different machine cycles is divided into a 1st data transfer unit 20a and a 2nd data transfer unit 20c. Both units 20a and 20c are controlled by a clock having the same cycle as that of the processors 1 and 3 which perform the transfer of data respectively. The control signals transferred to both units 20a and 20c are synchronized with each other via the synchronizing circuits 26a-26d so as to be coincident with the clock phase of the unit that receives the data. Then these synchronized control signals are latched and used. Thus the production interval is shortened for the data transfer requests. Furthermore the data transfer throughput can be improved without increasing the width of the data to be transferred.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data transfer system, and in particular, when a data processing system is configured by combining data processing devices with different machine cycles, The present invention relates to a data transfer method that allows data transfer between data processing devices at a high data transfer throughput.

[Conventional technology]

Conventionally, in a data processing system constructed by combining data processing devices with different machine cycles, data transfer between the plurality of data processing devices with different machine cycles constituting the data processing system is usually performed as follows. It will be done.

The transmitting data processing device that issues the data transfer request sends the data transfer request signal and the device address.

Send address data, transfer data, etc. On the other hand, after inputting the data transfer request signal to the first stage latch, the data processing device on the receiving side prevents malfunction due to a hazard signal that occurs when the rising (or falling) of the input pulse signal overlaps with the synchronized clock of the latch. Therefore, after the hazard signal latch prevention time has elapsed, the first stage latch output is set to 2.
Data transfer is performed by setting the address data and transfer data received in the rising differential signal of the output signal of this latch.

A specific example of such data transfer between data processing devices with different machine cycles is data transfer between an input/output control device and a main memory control device that constitute a data processing system. The former input/output controller is a device that controls a channel with a large machine cycle, and the latter main memory controller is a device that operates in synchronization with an instruction processor that has a small machine cycle, so the former is usually more efficient than the latter. The machine cycle is large.

FIG. 4 is a schematic block diagram of a data transfer device illustrating an example of a data transfer method for transferring data between data processing devices having different machine cycles. Moreover, FIG. 5 is a time chart of the data transfer device of FIG. 4.

This will be explained with reference to FIGS. 4 and 5. The A device 1, which is the first data processing device, is the B device 2, which is the data transfer device.
C unit of the second data processing device! The B device 2, which transfers data to the i23, may be included in and integrated with the C device 3.

Here, in order to explain the data transfer operation, a separately provided configuration is shown.

Device A 1 sends a data transfer request signal 10 to device B 2 from the REQ sending terminal. In conjunction with sending out this data transfer request signal, data signals 11 such as address data and transfer data are sent out from the DATA sending terminal.

Since the data transfer request signal 10 is an asynchronous signal in the B device 2, the first stage latch is After inputting to latch 12,
After the hazard signal latch prevention time has elapsed, it is set in the second stage latch 13. The setting timing of these latches is the operation at the rising edge of the SET signal based on the clock of the B device 2. The output from the latch 13 is turned into a one-cycle pulse signal 15 synchronized with the clock of the B device 2 by a rising differentiation circuit 14 . By this pulse signal 15, the data signal 11 to be transferred, such as transfer data, address data, and other control data sent from the DATA sending terminal of the A device 1, is set in the register 16. In FIG. 4, address data, transfer data, etc. are shown as a representative data signal 11 without distinction, and illustration of address registers and the like is omitted.

The transfer data signal is sent from the B device 2 to the C device 3 of the data transfer device by the B device 2 generated by the rising differential circuit 14.
A one-cycle pulse signal 15 synchronized with the clock of
It is sent to the REQ receiving terminal of the C device 3 as a data transfer request signal 17. Further, as the data signal 18, the data set in the register 16 is sent out. Data signal 11
is sent to the C device 3 via the B device 2, data transfer is performed, and when the processing of the transferred data received by the C device 3 is not completed and the next transfer data cannot be received, the data is transferred from the C device 3. The data transfer request issue suppression signal 19 is transmitted to the FU of the C device 3.
It is sent from the LL terminal to the FULL terminal of A device 1. The data transfer request issue suppression signal 19 is a signal that is set to logic II 1 tt when a data transfer request cannot be accepted.

Incidentally, as a known document related to an asynchronous signal synchronization method for data transfer by synchronizing asynchronous signals in this manner, there may be mentioned Japanese Utility Model Application Publication No. 53-60749.

[Problem to be solved by the invention]

By the way, in data transfer between data processing devices with different machine cycles as described above, there is a delay in the signal transmission line, and ultimately the data must be received in synchronization with the clock of the C device on the receiving side. For example, the pulse width of the data transfer request signal sent from device A cannot be made narrower than a predetermined limit. For example, the minimum value of the pulse width of such a data transfer request signal is determined by the following conditions.

(1) The pulse width of the data transfer request signal is 1
The interval is made wider than the interval between the rising edge of the set signal of the latch in the second stage and the falling edge of the subsequent set signal. This is because if it is narrow, this signal may not be able to be latched.

(2) The interval between issuance of the set signal of the first stage latch and the subsequent set signal of the second stage latch is more than the hazard prevention time, and the set signal of the second stage latch and the subsequent set signal of the first stage latch are Set signals should not overlap.

In such data transfer, in order to increase the data transfer throughput, it is necessary to narrow the pulse width of the data transfer request signal and make the issuance interval of the data transfer request signal closer. has a limit,
As mentioned above, the pulse width cannot be made narrower than a predetermined pulse width. Therefore, the data transfer throughput cannot be increased by a method of narrowing the pulse width of the data transfer request signal.

In this way, the pulse width of the data transfer request signal cannot be narrowed beyond a certain limit, so if it is necessary to increase the throughput during data transfer, the data width of the transfer data (simultaneously parallel There is no other way than to widen the bit width of the data to be transferred. However, increasing the data width of data transfer increases the amount of hardware and makes the device complex.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a data processing system that combines data processing devices with different machine cycles.
An object of the present invention is to provide a data transfer method capable of transferring data between a plurality of data processing devices at a high data transfer throughput.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

In order to achieve the above object, the present invention provides a data processing system configured by combining a plurality of data processing devices with different machine cycles, in which a first data processing device and a machine A first data transfer unit that is controlled by a clock that has the same cycle as the machine cycle of the first data processing device and a second data processing device that has a different cycle, and a clock that has the same cycle as the machine cycle of the second data processing device. A second data transfer unit controlled by a clock, and a control signal transferred between the first data transfer unit and the second data transfer unit are synchronized in accordance with the phase of the clock of the receiving side unit. The present invention is characterized in that a data transfer device is provided, and data is transferred between a plurality of data processing devices via the data transfer device.

[Effect]

According to the means, a first data processing device.

A first data processing device that is controlled by a clock having the same cycle as the machine cycle of the first data processing device and a second data processing device whose machine cycle is different from that of the first data processing device.
a second data transfer unit controlled by a clock having the same cycle as that of the second data processing device, and a control signal transferred between the first data transfer unit and the second data transfer unit. A data transfer device is provided which synchronizes and uses the signals according to the phase of the clock of the receiving unit. In this data transfer device installed between a plurality of data processing devices with different machine cycles, the inside of the device is divided into a plurality of units including a first data transfer unit and a second data transfer unit. It is configured to be controlled by a clock having the same cycle as the data processing device that performs the transfer. Further, the control signals passing through each unit are synchronized to match the clock phase of the unit receiving the transfer data, and are then latched and used.

By connecting the data processing devices via the data transfer device and performing data transfer, each unit of the data transfer device and each data processing device of the system that transfers data are the same. It is controlled by a periodic clock and has the same machine cycle. For this reason, each data processing device in the system performs
Data transfer request issuance intervals can be made closer.

In addition, between each unit of the data transfer device, the data transfer control signal is synchronized with the clock phase of each unit and then latched and used, so data transfer is possible without increasing the data width of the transferred data. Throughput can be improved.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

Note that throughout the explanation of the embodiments, the same elements are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a block diagram showing the configuration of a data transfer device according to an embodiment of the present invention. In Figure 1, the first
A device B, which is a data transfer device, is connected between A device 1, which is a data processing device, and C device 3, which is a second data processing device.
A device 20 is provided, and data is transferred via this B device 20.

Inside the B device 20, a first data transfer unit 20a
and a second data transfer unit 20c. The first data transfer unit 20a is controlled by a clock having the same cycle as the A device 1 of the first data processing device, and operates in the same machine cycle. Further, the second data transfer unit 20c is controlled by a clock having the same cycle as the C device 3 of the second data processing device, and operates in the same machine cycle. Here, the machine cycle of the A device 1 and the machine cycle of the C device 3 are different.

The data transfer request signal 10a from the A device 1 is sent to the latch 29.
Once set, the request acceptance is input to the circuit 21. A latch 22a in the circuit 21 accepts requests.

Outputs from latches 22b, 22c, and 22d are respectively input, and latches 22a, 22b, and 22
c, 22d are data registers 23a, 23b
, 23c, and 23d each indicate whether or not they are in use. When the data register is in use, the output of the latch becomes "1". Although registers for setting address data and other data are also provided, they are not shown in FIG. 1 to avoid complexity.

For request reception, signals are output from the circuit 21 through four signal lines 24a, 24b, 24c, and 24d.
It is output by. These signal lines 24a, 2
4b, 24c.

24d, one of the outputs becomes logic 41111 depending on the usage status of the data register. To explain more specifically, the request reception circuit 21 consists of four AND gates, latches 22a, 22b, 22c, 22.
Depending on the logic of the output of d, the signal line 24a.

One of 24b, 24c, and 24d is logic '1
country.

The outputs of the signal lines 24a, 24b, 24c, 24d are connected to the latches 22a, 22b, 22c,
22d and data registers 23a and 23b.
, 23c, and 23d. This results in
Data signal 11 from the DADA terminal is read into the data register. Moreover, at the same time, the signal lines 24a, 24
The outputs of b, 24c, and 24d are sent to pulse width expansion circuits 25a, 25b, 25c, and 25, respectively.
d and synchronous circuits 26a, 26b, 26c,
Via 26d, latches 27a, 27b,
27c and 27d.

Pulse width expansion circuits 25a, 25b, 25c,
25d is the subsequent synchronous circuit 26a, 26b,
It is provided to widen the pulse width of the signal input to 26Q and 26d.

Each synchronous circuit 26a, 26b, 26c,
The configuration of 26d is similar to the circuit shown in FIG.
It consists of two latches and a rising differential circuit. The outputs of the synchronization circuits 26a, 26b, 26c, and 26d are synchronized with the clock that controls the second data transfer unit 20c, and the pulse width is one machine cycle of the C device 3.

The outputs of the latches 27a, 27b, 27c, and 27d are input to the request selection circuit 28. The request selection circuit 28 includes latches 27a, 27b, 27c,
27d and the counters 30a, 30b,
The outputs of 30c and 30d and the output of latch 31 are input. The output from the request selection circuit 28 is the latch 3
2a, 32b, 32c, and 32d. The request selection circuit 28 operates on a first-in, first-out basis so that the waiting time for passing through the request selection circuit is reduced.
First out). This request selection circuit 2
Reference numeral 8 selects and outputs the received request signal using a control table as shown in FIG.

FIG. 2 is a diagram illustrating a control table used for processing the selection procedure of the request selection circuit. The selection procedure of the request selection circuit will be explained with reference to FIG.

If there are multiple data transfer requests, i.e. latch 2
7a, 2? b, 27c, 2? Logic “1” in d
'', the counters 30a and 30b
, 30c, and 30d, the requests that have been waited for most times are selected. If there are two or more requests with the same number of wait times, the requests are selected in a preset order.

Counters 30a, 30b, 30c, 30d
are the respective signal lines 24a, 24b, 24c,
It is provided in response to the request of 24d, and is incremented by 1 when a request other than the own request is selected, and is reset at the same time as the corresponding latch when the own request is selected. Ru.

When the request selection circuit 28 selects a certain data transfer request, the selected output is sent to the latches 32a, 32b, 32.
c.

The 0 selection output input to 32d causes the latch 32a.

When a logic "1" is set in one of 32b, 32c, 32d, latches 32a, 32b, 32
The output signals of c and 32d are passed through the OR gate 33,
The data is transferred to the C device 3 as a data transfer request 17a.

In addition, latches 32a, 32b, 32c, 3
2d output signals 34a, 34b, 34c, 34
d, the selector 35 selects the data register 23a,
One of the outputs from 23b, 23c, and 23d is selected, set in the - register 36, and then transferred to the C device 3 of the second data processing device. Address data and other data are similarly transferred to C device 3, but this path is not shown.

Output signals 34a, 34b, 34c, 3 from latches 32a, 32b, 32c, 32d
4d are synchronization circuits 37a, 37b, and 37c provided in the first data transfer unit 20a.

Via 37d, latches 22a, 22b, 2
Reset 2c and 22d. The data transfer request suppression signal 19c from the C device 3 of the second data processing device is
When a data transfer request cannot be accepted, the logic is set to "1n. This data transfer request inhibit signal 19c is set in the latch 31 of the second data transfer unit 20c and applied to the request selection circuit 28.

The data transfer request issue inhibition signal 19b from the B device 20 is sent from the first data transfer unit 20a. This data transfer request issue suppression signal 19b is set to logic (11++) when a data transfer request cannot be accepted.The data transfer request issue suppression signal 19b is output to the latch 22a,
When three or more outputs of outputs 22b, 22c, and 22d are logic "1", logic "1"
is output as

FIG. 3 is a time chart showing the operation of the data transfer device according to an embodiment of the present invention. The time chart in FIG. 3 shows that a data transfer request is issued continuously from A device 1, passes through B device 20, which is a data transfer device, and then is sent to C device 3.
This shows how it is transferred to. Also shown here are the first data transfer unit 20a and the second data transfer unit 20a in the B device 20.
The data transfer units 20c are shown operating with different clocks. Comparing the time chart in FIG. 3 with the time chart in FIG. 5, the interval between data transfer requests issued by device A of the data processing device is narrower in the time chart in FIG. /2. This indicates that the data transfer throughput is doubled.

In the above explanation, A device 1. Regarding data transfer in which data is transferred in the order of B device [20 and C device 3].

Although described above, data transfer in the reverse direction is performed in the same manner using a similar configuration. Furthermore, it is also possible to connect not only the C device but also other data processing devices such as the D device and the E device to the B device 20.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As explained above, according to the present invention, during data processing in different machine cycles, the inside of the device is divided into a plurality of units, and each unit uses the same clock as the data processing device that transfers data. Since data transfer is performed through an operating data transfer device, both the data processing device issuing the data transfer request and the data processing device receiving the data transfer request control the internal control of each device. Data transfer processing can be performed by controlling machine cycle pitch. Thereby, data transfer throughput can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data transfer device according to an embodiment of the present invention. FIG. 2 is a diagram explaining a control table used for processing the selection procedure of the request selection circuit, FIG. 3 is a time chart showing the operation of the data transfer device according to an embodiment of the present invention, and FIG. , a schematic block diagram of a data transfer device illustrating an example of a data transfer method for transferring data between data processing devices with different machine cycles. FIG. 5 is a time chart of the data transfer device of FIG. 4. In the figure, 1, 3... data processing device, 2. io...'
Data transfer device, 12.13...Latch, 14...
Rising differential circuit, 16.23a, 23b, 23
c, 23d, 36-register, 20a...first
data transfer unit, 20c...second data transfer unit, 21...request reception circuit, 26a. 26b, 26c, 26d2, 37a, 37b, 37c,
37cl=synchronous circuit, 28... request selection circuit, 35.
··selector.

Claims (1)

[Claims] 1. In a data processing system configured by combining a plurality of data processing devices with different machine cycles, a first data processing device and a second data processing device with a different machine cycle from the first data processing device. In between, a first data transfer unit controlled by a clock having the same period as the machine cycle of the first data processing device and a second data transfer unit controlled by a clock having the same period as the second data processing device. a data transfer device that synchronizes a control signal transferred between the unit, the first data transfer unit, and the second data transfer unit in accordance with the phase of the clock of the receiving unit; A data transfer method characterized by transferring data between multiple data processing devices via a device.